Sounak Banerji

Design, Modeling, and Characterization of Embedded Capacitor Networks for Core Decoupling in the Package

Embedded passives are gaining in importance due to the reduction in size of electronic products. Capacitors pose the biggest challenge for integration in packages due to the large capacitance required for decoupling high performance circuits. Surface mount discrete (SMD) capacitors become ineffective charge providers above 100 MHz due to the increased effect of loop inductance. This paper focuses on the importance of embedded capacitors above this frequency. Modeling, measurements, and model to hardware correlation of these capacitors are shown. Design and modeling of embedded capacitor arrays for decoupling processors in the midfrequency band (100 MHz-2 GHz) is also highlighted in this paper.

Improvements in Noise Suppression for I/O Circuits Using Embedded Planar Capacitors

The performance of embedded planar capacitors in noise suppression of input/output (I/O) circuits and improvements in board impedance profile have been investigated in this paper. Simultaneous switching noise (SSN) is a critical issue in todays systems and this paper shows performance improvements by introducing thin planar embedded capacitors in the board stack up. Measurement and modeling results by including the effects of transmission lines and the power ground plane pairs in the board stack up in the gigahertz range quantify the performance of the embedded capacitors.

The role of stiff base substrates in warpage reduction for future high-density-wiring requirements

The role of warpage on future high density wiring requirements is investigated. These studies also show the impact of the gap between mask and the substrate arising out of warpage on the width of fine lines when vacuum cannot reduce the effect of warpage. For 100 micron wide lines, substrates with warpage greater then 50 microns are found to result in 30% error in the actual transferred pattern, while warpage greater than 200 microns results in the complete elimination of photoresist openings. The via-pad misalignment for a 300 mm substrate was measured to be 116 microns for FR4 substrate while the value is less than 25 microns for AlN. The % displacement, defined as the distance between the via center and pad center normalized with respect to the pad diameter, is hence more than 25% in case of a warped substrate, while it is found to be less than 10% for stiffer substrates. Hence, as feature size becomes smaller, accurate translation of mask features on to the substrate during photolithography will be limited by the warpage of the substrate and hence stiffer substrates are required to meet next-generation high-density wiring needs.

Warpage-induced lithographic limitations of FR-4 and the need for novel board materials for future microvia and global interconnect needs

The effect of warpage on lithographic capabilities of organic circuit boards with multilayered thin film buildup was investigated. Two to six epoxy layers were built on various candidate boards to characterize the warpage and correlate it with analytical models. Underlying mechanisms were investigated and novel parameters defined to correlate warpage with photodefinition of ultrafine lines and vias on the board. Based on the experiments, warpage specifications for the multifunctional multilayered requirements in a proposed system-on-package (SOP) structure were defined. Experimentally validated FEM models were used to estimate the warpage during the multilayered buildup. Results show that FR-4 is not suitable for future high-density packaging needs and underscore the need for stiffer ceramic-based circuit board materials as replacement for FR-4