Kan-Hsueh Tsai

Challenges and opportunities for HfO X based resistive random access memory

The binary oxide based resistive memories showing superior electrical performances on the resistive switching are reviewed in this paper. The status and challenges of the HfOX based resistive device with excellent memory properties are presented. Several future challenges for the filamentary type switching device are also addressed.

Novel Defects-Trapping

The dependence of resistive switching of Ta/TaOX/HfOX device governed by general filamentary or novel defects-trapping mechanism on the operation current is demonstrated in this letter. The device with stable resistive switching, high nonlinearity, and robust self-compliance ~ 1 μA is demonstrated, which can be integrated in the vertical RRAM structure. Based on constant current density switching ( ~ 103 A/cm2) governed by defects-trapping transport, where the low and high resistance states attributed to the resistance of Ta/TaOX layer and device initial state, the switching current reduction by scaling down the cell size is proposed in transition metal oxide RRAM.

{\rm TaO}_{\rm X}/{\rm HfO}_{\rm X}

A new two-transistor embedded resistive RAM (RRAM) cell with fully Taiwan Semiconductor Manufacturing Company 28-nm CMOS logic compatible process is reported. The new 28-nm logic compatible RRAM cell consists of two logic standard high- k metal gate (HKMG) CMOS transistors with a composite resistive gate dielectric of TiN/ HfO2/SiO2/Si as a resistive memory storage node. Using one of the transistor gates as a source line in RRAM SET/RESET operation, the resistive memory states can be efficiently read and sensed by selecting the other transistor gate and its corresponding bitline. Therefore, the new 2T embedded RRAM cell has realized a logic nonvolatile memory (NVM) solution with cost effective, and fully compatible with 28-nm HKMG CMOS logic platforms. Besides, through adapting the existing high- K gate dielectric in the RRAM cell, the embedded memory cell does not need any additional deposition of resistive film or extra process steps and it will be very scalable and compatible with the fast progress of CMOS technologies in embedded NVM applications. Furthermore, its low voltage requirement makes this cell conveniently fit in logic intellectual properties and circuits for local data storages or level trimming devices on system-on-chip logic NVM products.

RRAM With Reliable Self-Compliance, High Nonlinearity, and Ultra-Low Current

Ti/HfOx-based resistive random access memory (RRAM) has been extensively investigated as an emerging nonvolatile memory (NVM) candidate due to its excellent memory performance and CMOS process compatibility. Although the importance of the role of the Ti buffer layer is well recognized, detailed understanding about the nature of Ti thickness-dependent asymmetric switching is still missing. To realize this, the present work addresses the effects of Ti buffer layer thickness on the switching properties of TiN/Ti/HfOx/TiN 1T1R RRAM. Consequently, we have demonstrated a simple strategy to regulate the FORMING voltage, leakage current, memory window, and decrease the operation current, etc. by varying the thickness of the Ti layer on the HfOx dielectrics. Accordingly, controllable and reliable bipolar, complementary, and reverse bipolar resistive switching (BRS, CRS, and R-BRS) properties have been demonstrated. This work also provides the direction to avoid unwanted CRS properties during the first RESET operation by decreasing the FORMING voltage. Furthermore, the memory device shows good nonvolatility at ∼1 μA programming current by selecting a proper thickness of Ti buffer layer. To achieve reliable BRS properties for low power application, the operation current has been further optimized, whereas the memory device shows pulse endurance of more than 7 million cycles at a low pulse width of 50 ns and excellent data retention properties of more than 40 h at 150 °C measurement temperature.

28-nm 2T High-

Resistive random access memory (RRAM) is a promising new non-volatile memory technology capable of operating at low power as well as high speed. Although RRAM is capable of lower energy consumption and substantially more cycles than Flash memory, comprehending and maintaining its ability to store data under stressed conditions remains the key challenge for mainstream acceptance. This in large part is due to the filamentary nature of the RRAM element at the nanoscale. A filament-based resistive memory is based on the formation of current-conducting path (filaments) from defects, e.g., oxygen vacancies. The defects often lead to trap-limited current conduction. Without proper process control or RESET algorithms, unwanted defects may be added near the filaments under device stress, further aggravating the resistance instabilities.

K

Owing to NAND flash technology facing its scaling limit, resistive random access memory (RRAM) with simple film stack and no cross coupling issue between cells is a promising candidate for future high density memory application [1,2]. The 1TnR architecture with 3D vertical RRAM (VRRAM) structure realizes ultra-low bit cost for high compact density array [3,4]. However, this novel 1TnR structure and processes have not been proved yet. To meet requirements of VRRAM array operation, the nonlinear resistive memory with an excellent self-compliance and low current operation is indispensable [5,6]. A large voltage margin for the device operated with compliance current (ΔVCOMP) and high nonlinearity for the device at low resistance state (LRS) with reliable read voltage should be addressed.

Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

The scalability issue of 1T-1R Ti/HfOx BRM, which is resulted from the interaction between BRM and transistor, is demonstrated. While a sufficiently lower Vforming can mitigate the RP, an alternative buffer layer Ta is also proposed to further scale the 1T-1R HfOx based BRM.

The Role of Ti Buffer Layer Thickness on the Resistive Switching Properties of Hafnium Oxide-Based Resistive Switching Memories

A Ta ultra-thin metal layer was treated by O2 plasma at low temperature to form TaOx, which severs as a resistive element or internal resistor. The low current operated Ta/TaOx/HfOx and Ta/TaOx/AlOx devices exhibit self-compliance, good LRS nonlinearity (>40), robust retention at 85 °C, and enough endurance (>1000). A plausible mechanism is proposed. The low temperature plasma oxidation of Ta layer is demonstrated an potential process for vertical RRAM with self-compliance and low current operation of 5 μA.

Resistance instabilities in a filament-based resistive memory

The design, cost, and the operation methodology in the 2-terminal and 3-terminal VRRAM devices are studied. The real 3D vertical-contact RRAM devices are also demonstrated and the devices showed good memory performance. A self-rectifying device is proposed to suppress the sneak current in the VRRAM.

Highly robust self-compliant and nonlinear TaO X /HfO X RRAM for 3D vertical structure in 1TnR architecture

This study demonstrated a nonvolatile look-up table (nvLUT) that involves using resistive random access memory (ReRAM) cells with normally-off and instant-on functions for suppressing standby current. Compared with the conventional static random access memory (SRAM)-magnetoresistive random-access memory (MRAM)-hybrid LUTs the proposed ReRAM-based two-input nvLUT circuit decreases the number of transistors and the area of nvLUT by 79% and 90.4%, respectively. The areas of the two- and three-input ReRAM nvLUTs are 11.5% and 74.2% smaller than the other MRAM-based two-input and PCM-based three-input LUTs, respectively. Because of the low current switching and high R-ratio characteristics of ReRAM, the proposed ReRAM-based nvLUT achieves 24% less power consumption than that of SRAM-MRAM-hybrid LUTs. The functionality of the fabricated adder of the three-input ReRAM nvLUT was confirmed using an HfOx-based ReRAM and a 0.18-μm complementary metal-oxide semiconductor with a delay time of 900 ps.