Pei-Yi Gu

Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity

A 30×30 nm2 HfOx resistance random access memory (RRAM) with excellent electrical performances is demonstrated for the scaling feasibility in this work. A 1 Kb one transistor and one resistor (1T1R) array with robust characteristics was also fabricated successfully. The device yield of the 1 Kb array is 100%, and the endurance for these devices can exceed 106 cycles by a pulse width of 40 ns. Two effective verification methods, which make a tight distribution of high resistance (RHIGH) and low resistance (RLOW) are proposed for the array to ensure a good operation window. A thin AlOx buffer layer under the HfOx layer was adopted to enhance the read disturb immunity. Without large parasitic capacitance, the 1T1R RRAM devices exhibit excellent program(PGM)/erase(ERS) disturb immunity.

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1–3], MRAM [4–5], and resistive RAM (RRAM) [6–8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

Evidence and solution of over-RESET problem for HfO X based resistive memory with sub-ns switching speed and high endurance

The memory performances of the HfOX based bipolar resistive memory, including switching speed and memory reliability, are greatly improved in this work. Record high switching speed down to 300 ps is achieved. The cycling test shed a clear light on the wearing behavior of resistance states, and the correlation between over-RESET phenomenon and the worn low resistance state in the devices is discussed. The modified bottom electrode is proposed for the memory device to maintain the memory window and to endure resistive switching up to 1010 cycles.

Challenges and opportunities for HfO X based resistive random access memory

The binary oxide based resistive memories showing superior electrical performances on the resistive switching are reviewed in this paper. The status and challenges of the HfOX based resistive device with excellent memory properties are presented. Several future challenges for the filamentary type switching device are also addressed.

Novel Defects-Trapping

The dependence of resistive switching of Ta/TaOX/HfOX device governed by general filamentary or novel defects-trapping mechanism on the operation current is demonstrated in this letter. The device with stable resistive switching, high nonlinearity, and robust self-compliance ~ 1 μA is demonstrated, which can be integrated in the vertical RRAM structure. Based on constant current density switching ( ~ 103 A/cm2) governed by defects-trapping transport, where the low and high resistance states attributed to the resistance of Ta/TaOX layer and device initial state, the switching current reduction by scaling down the cell size is proposed in transition metal oxide RRAM.

{\rm TaO}_{\rm X}/{\rm HfO}_{\rm X}

The effect of operation current on the high-resistance state and the endurance for the HfOx-based resistive device is comprehensively studied. Due to the current overshoot by the parasitic capacitances, an excess current leakage for the high resistance state of the 1R device after the forming and SET stages is observed. The accelerated degradation of the high-resistance state for the HfOx device undergoing a high-operation-current stage is revealed for the first time. As the compliance current increases beyond 500 μA, the resistance of the high-resistance state of the device deceases drastically. A possible scenario about the correlation between the high-resistance state and the compliance current based on the filament model is proposed. By suppressing the current overshoot with the 1T1R device, the high-resistance state (>; 1 MΩ) and excellent endurance (>; 108 cycles) for the HfOx resistive memory are demonstrated.

RRAM With Reliable Self-Compliance, High Nonlinearity, and Ultra-Low Current

Resistive random access memory (RRAM or ReRAM) is a non-volatile memory (NVM) technology that consumes minimal energy while offering sub-nanosecond switching. In addition, the data stability against high temperature and cycling wear is very robust, allowing new NVM applications in a variety of markets (automotive, embedded, storage, RAM). Based on sudden conduction through oxide insulators, the characteristics of RRAM technology have still yet to be fully described. In this paper, we present our current understanding of this very promising technology.

Robust High-Resistance State and Improved Endurance of

In this paper, statistical measurements on the retention behavior of the stable HfOBx-based RRAM under various thermal/voltage/cycling stresses are investigated. Testing results show that, data retention of high resistance state (HRS) of a RRAM is insensitive to temperature and cycling-aging. An empirical equation involving the voltage/thermal/cycling-stress acceleration is given for lifetime prediction. 10 years lifetime can be obtained with a constant read voltage of 0.2 V even at 160 °C. Also the set time of the RRAM extrapolated by the empirical equation coincides with the experiment value. In addition, the shallow Weibull slope of the retention time can be improved when the variations of the initial resistance is well controlled.

\hbox{HfO}_{X}

Although a significant effort was made recently in the development of binary oxide based resistive memory (RRAM) [1,2], reliability issue is still the most concern, but less addressed [3,4]. By stressing the device in high resistance state (HRS) with constant voltage of the same bias polarity during SET process, the disturbed time is found to exhibit extreme low Weibull slope (~0.3). This characteristic can drastically shrink the reliability margin for reading process [4]. Inserting a thin Al2O3 between the transition metal oxide and bottom electrode was proposed previously to improve read disturb immunity at room temperature [4]. However, the effect of high temperature (125°C) on the read disturb of this stacked layer (HfOx/Al2O3) has not yet been studied.

Resistive Memory by Suppression of Current Overshoot

The impact of engineered Ti at the interface of HfO x /TiN on the performance of a HfO x resistive memory (RM) is investigated. Microstructures of 5 nm thick HfO x films seem insensitive to the bottom layer (BL) with/without Ti. The switching behavior of the HfO x RM depends on the position and the thickness of the Ti layer. More oxygen atoms in HfO x films are captured during the deposition of a Ti overlayer; this result leads to a Ti/HfO x device with lower forming voltage and initial resistance. A thick Ti BL (>30 nm) results in a HfO x /Ti device with yield of 100% and superior endurance (> 10 6 cycles).