Tapio Rapinoja

Multitone Fast Frequency-Hopping Synthesizer for UWB Radio

A fast frequency-hopping six-band local oscillator signal generator is described in this paper. Targeted for a Wi-Media ultra-wideband radio transceiver, it offers operation in mandatory band group 1 and in extensional band group 3. The circuit entity consists of three parallel phase-locked loops (PLLs), each including two voltage-controlled oscillators, one per band group, and a signal multiplexer for fast frequency selection. A broadband poly-phase RC filter is used for in-phase/quadrature generation. Furthermore, the synthesizer generates the clock signal for analog-to-digital converters by mixing the signals from the first and third PLL. The circuit was fabricated in a 0.13- mum CMOS process and it consumes 32 mA from a 1.2-V supply. It achieves 2-ns frequency settling time with a 3-MHz hopping rate.

A Digital Frequency Synthesizer for Cognitive Radio Spectrum Sensing Applications

This paper presents a wideband digital frequency synthesizer architecture targeted for spectrum sensing applications. The proposed frequency synthesizer architecture is based on digital period synthesis (DPS), which inherently can achieve a wide operational bandwidth, extremely high-frequency resolution, and an instantaneous settling time with low power and area consumption. The performance of DPS and its fundamental limitations are analyzed in this paper. The frequency synthesizer was implemented in a 65-nm CMOS process and it occupies an active area of 0.12 mm2 . The frequency range of the synthesizer is from 0.1 to 4.267 GHz with a frequency resolution of 0.025-5.38 Hz. In this frequency range, the power consumption is between 3.6-8.4 mW.

A WiMedia UWB receiver with a synthesizer

This paper describes a direct-conversion receiver for WiMedia UWB applications. The receiver consists of separate BG1 and BG3 LNAs including a 2.4-GHz notch filter, quadrature mixers, a base-band gm-C low-pass filter with variable gain, and a fast-hopping synthesizer. The UWB receiver is targeted for a mobile handset and therefore special emphasis has been placed on the reduction of interferers. The receiver achieves 60-dB gain, noise figure less than 6.2 dB, LO settling time of less than 3 ns and DC current consumption of 137 mA from a 1.2-V supply for BG1 operation mode. The chip was fabricated using 65-nm standard CMOS process.

A digital frequency synthesizer for cognitive radio spectrum sensing applications

This paper presents a wideband digital frequency synthesizer architecture targeted for spectrum sensing applications. The proposed frequency synthesizer architecture is based on digital period synthesis (DPS), which inherently can achieve a wide operational bandwidth, extremely high-frequency resolution, and an instantaneous settling time with low power and area consumption. The performance of DPS and its fundamental limitations are analyzed in this paper. The frequency synthesizer was implemented in a 65-nm CMOS process and it occupies an active area of 0.12 mm2 . The frequency range of the synthesizer is from 0.1 to 4.267 GHz with a frequency resolution of 0.025-5.38 Hz. In this frequency range, the power consumption is between 3.6-8.4 mW.

A Low-Power Phase-Locked Loop for UWB Applications

This paper describes a low-power phase-locked loop (PLL) design for multiband-OFDM UWB synthesizer implemented in a 0.13-mum CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of -54 dBc and in-band phase noise of -78 dBc/Hz

Behavioral Model based Simulation Methods for Charge-Pump PLL's

This paper discusses the ubiquitous problem of extremely long simulation times in transistor-level design of phase-locked loops (PLL). Methods for reducing time-domain simulation times arc presented. A Matlab simulation environment has been developed for the PLL simulations. Moreover, Spice macromodels for PLL building blocks have been introduced for achieving shorter time-domain Spice simulations. With these tools fast behavioural simulations, which are needed when dimensioning the PLL parameters, can be done in the Matlab environment, and the functionality of transistor level design of PLL blocks can be verified by a time-domain analysis in a reasonably short time

Fractional-N open-loop digital frequency synthesizer with a post-modulator for jitter reduction

This paper presents a 0.4 to 2.1 GHz open-loop fractional-N multiplying delay-locked loop based frequency synthesizer in 65 nm CMOS. The proposed frequency synthesizer architecture is based on Digital Period Synthesis that features wide frequency range, fine frequency resolution, instantaneous frequency switching and is capable to provide several independent outputs. An inherent challenge of fractional-N synthesis is a notable deterministic jitter. In this paper we present a high-speed direct delay modulation circuit (DDM) that provides over ten-fold reduction in deterministic jitter over the entire frequency range. The measured deterministic period jitter, related to the fractional mode operation, is reduced from 51 ps to 4 ps by using the DDM. Furthermore, in this paper we demonstrate, for the first time, how the implemented synthesizer can produce two totally independent outputs at different frequencies.

A 0.3-to-8.5GHz frequency synthesizer based on digital period synthesis

This paper presents a wide-band digital frequency synthesizer based on digital period synthesis (DPS). As a direct frequency synthesis method, the DPS architecture achieves inherently wide operational band, high frequency resolution and instantaneous settling. The frequency synthesizer, including reference delay-locked loop (DLL), DPS unit, and frequency multiplying DLL, was implemented in a 65-nm CMOS process and it occupies an active area of 0.3 mm2. The implemented frequency synthesizer covers a frequency range from 0.3 GHz to 8.5 GHz with 1 Hz frequency resolution, 550 fs integrated jitter, and 0.9 μs settling time.

Implementation of all-digital wideband RF frequency synthesizers in 65-nm CMOS technology

This paper presents two all-digital RF frequency synthesizers implemented in 65-nm CMOS: a digital period frequency synthesizer and an all-digital phase-locked loop. This paper is especially focused on the implementation issues and practical challenges of digital frequency synthesizers for wideband radio systems. Moreover, the paper presents implementations and experimental results of these two frequency synthesizers targeted for cognitive radio spectrum sensing applications.

Spectral purity analysis of integer-N PLL

This paper describes a method for mutual phase noise and spurious tones analysis of integer-N phase locked loop (PLL). With this method both contributions of individual phase noise sources and effects of parameter dimensioning, on the spectral purity, can easily be recognized. Furthermore, a transistor-level analysis example is given to clarify and to illustrate the spectral purity optimization.