Siau Ben Chiah

Surface-Potential Solution for Generic Undoped MOSFETs With Two Gates

We present a rigorously derived analytical Poisson solution for undoped semiconductors and apply the general solution to generic MOSFETs with two gates, unifying different types such as silicon-on-insulator (SOI) and symmetric and asymmetric double gate (s-DG and a-DG) structures. The Newton-Raphson method is used to solve surface-potential equations resulting from the application of boundary conditions to the general Poisson solution, with an initial guess that is very close to the exact solution. The universal initial guess can be used as an approximate explicit solution for fast evaluation, while the iterative solution can be used for benchmark tests. The results demonstrate the unification of surface-potential solutions having an accuracy of 10-15 V for SOI, a-DG, and s-DG MOSFETs, which are achieved within two to six iterations. Furthermore, the explicit solution yields less than 3.5% error for back-to-front-gate oxide thickness ratios larger than 25

A Compact Model Satisfying Gummel Symmetry in Higher Order Derivatives and Applicable to Asymmetric MOSFETs

This paper presents a new concept for the MOSFET saturation voltages at the drain and source sides referenced to bulk, and applies them to the popularly used smoothing functions for the effective drain-source voltage (Vds,eff ). The proposed model not only builds in physically all the terminal-bias variations, but is also extended to include source/drain asymmetry in real devices in a single-core compact model. The new model resolves a key bottleneck in existing models for passing the Gummel symmetry test (GST) in higher order derivatives, which has to be traded off for the geometry-dependent Vds,eff smoothing parameter. The complete drain-current model, including the effects of velocity saturation and overshoot as well as source/drain series resistance, has also been reformulated with the same ldquobulk-referencingrdquo concept. It is shown that the proposed model passes the GST in all higher order derivatives without any constraint on the value of the smoothing parameter. It also demonstrates potential extension to modeling asymmetric MOSFETs, which is becoming an important model capability.

Single-piece polycrystalline silicon accumulation/depletion/inversion model with implicit/explicit surface-potential solutions

A single-piece analytical equation for the surface potential at the polycrystalline-silicon (poly-Si) gate of a metal-oxide-semiconductor field-effect transistor is presented, which accounts for the poly-accumulation, poly-depletion, and poly-inversion effects. It is shown that the model accurately describes the physical behavior of the surface potentials, gate charge, and capacitance, with smooth transitions, which has been verified with iterative, explicit, and numerical solutions. The proposed model can be used in implicit or explicit surface-potential-based formulations.

A Comprehensive Compact Model for GaN HEMTs, Including Quasi-Steady-State and Transient Trap-Charge Effects

A comprehensive scalable trap-charge model for the dc and pulsed I-V modeling of GaN high electron-mobility transistor is presented. While interface traps are considered for dc I-V modeling, surface states and traps in the AlGaN barrier and GaN buffer are considered for the pulsed I-V model. A surface-potential-based model is presented for interface traps, which is then adapted to the current model for the dc modeling. For the pulsed I-V modeling, a semiempirical approach is proposed for gate lag as well as both gate-lag and drain-lag conditions. The model is able to capture the effects of gate (Vgq) and drain (Vdq) quiescent biases as well as the stress time (TOFF), and is validated with both numerical simulation and measurement data. Finally, for the accurate transient simulations in switching applications, the emission of electrons is also modeled in Verilog-A using an asymptotic solution of a differential equation, which can be a better alternative to that of the RC subcircuit approach.

Extraction of physical parameters of strained silicon MOSFETs from C-V measurement

This paper presents a methodology for extraction of the physical parameters of strained-silicon MOSFET from one capacitance-voltage (C-V) measurement based on physics-based compact model and conventional C-V characterization techniques. The extracted physical parameters (such as strained-silicon layer thickness and doping as well as conduction band offset) are used to create a numerical (Medici) device structure, from which the simulated C-V data is compared with the measured data as well as that from the compact model (Xsim), which validates the extraction technique. The proposed approach provides a simple yet physical means to probe into strained-silicon MOSFFET structures useful for characterize and model these devices, which are emerged as promising candidates for the enhancement and extension to conventional bulk-Si CMOS technology.

Source-drain symmetry in unified regional MOSFET model

This letter investigates major sources of asymmetry in a MOSFET compact model by comparing source versus bulk reference in the drain current, effective field, and effective mobility equations. Contrary to the general belief that a regional threshold voltage (V/sub t/)-based model may pose a symmetry problem, we demonstrate that even with the simple source-extrapolated V/sub t/-based model, it can be symmetric if the drain current and the effective transverse field are derived with bulk as the reference, and the lateral-field effective mobility are properly modeled.

Compact gate-current model based on transfer-matrix method

We present a compact gate-current model based on the scattering matrix method for metal-oxide-semiconductor devices. The analytical integration of the tunneling current over the incident energy is simplified by making use of the single tunneling energy approximation, and the model error is further reduced by introducing different effective conduction band edges for the supply function and for the transmission coefficient function. Results calculated by the proposed model agree with the experimental data with satisfactory accuracy.

Compact Fermi potential model for heterostructure HEMTs with rectangular quantum well

Compact models for high electron-mobility transistors (HEMTs) with triangular-potential-wells have been in development since the past few years. Double heterostructure HEMTs with rectangular-quantum-wells are also gaining importance due of their high mobility characteristics. Triangular-well model fails to capture the physics of double heterostructure devices. This paper presents a new physics based compact Fermi potential model for HEMTs with rectangular-well. It is validated with the coupled Poisson-Schrödinger based exact (numerical) solutions. The model is shown to accurately capture the Fermi-potential in the subthreshold, weak inversion, and strong inversion regions. The scalability of the model for device physical parameters is also presented. The proposed model can be used to simulate the Id-Vd and Id-Vg characteristics of double heterojunction HEMTs with rectangular-well.

Compact Zero-Temperature Coefficient Modeling Approach for MOSFETs Based on Unified Regional Modeling of Surface Potential

A compact zero-temperature coefficient (ZTC) modeling approach is demonstrated for generic MOSFETs. Instead of manually extracting ZTC points through <i>C</i>-<i>V</i> or <i>I</i>-<i>V</i> data over a range of operating temperatures, the ZTC model marks the cross-over ZTC points by Newton-Raphson solutions to the ZTC voltages based on the compact charge/current models. It calculates the ZTC voltages in the accumulation (<i>V</i>_ztc,sa) and depletion (<i>V</i>_ztc,ds) regions based on the unified regional modeling of surface potential for the gate capacitance at zero drain bias (<i>V</i>_ds=0). It is extended to the ZTC voltage (<i>V</i>_ztc,ds) for gate capacitance in the depletion and saturation regions at any <i>V</i>_ds, and the ZTC voltage (<i>V</i>_ztc) for drain current in the linear and saturation regions at any <i>V</i>_ds. The proposed approach can be adopted to create a process window with constant ZTC contours for different process parameters, such as body doping and gate-oxide thickness at any drain biases. The process windows provide useful information in determining the optimum process parameters and operating voltages for circuit design in ruggedized electronics that operate at high-temperature conditions.

Implicit Analytical Surface/Interface Potential Solutions for Modeling Strained-Si MOSFETs

A new technique for calculating surface and interface potentials in heterostructure MOSFETs such as strained-Si/SiGe using an internal iteration approach is presented. It is based on the unified regional approach with coupled iterative potential solutions at the surface and heterostructure interface, and it has been applied to modeling strained-Si/SiGe MOSFETs charge and capacitance in all bias regions, scalable for Ge mole fraction, strained-Si and SiGe layer thicknesses and doping. The formulations are shown for a buried-channel nMOSFET, and the approach to the solutions is generic to all heterostructures, which exhibit confinement of carriers at the different interfaces