Masahiro Kiyotoshi

Chemical Vapor Deposition of Ru and Its Application in (Ba,Sr)TiO3 Capacitors for Future Dynamic Random Access Memories

Ru films were fabricated by chemical vapor deposition using Ru(C5H5)2 and O2. The deposition of Ru film was controlled by the surface reaction kinetics as the rate limiting step with activation energy of 2.48 eV below 250°C and by the mass transport process above 250°C. Ru films had a polycrystalline structure and showed low resistivity of about 12 µΩcm. Ru films deposited at 230°C showed excellent step coverage. We applied Ru films prepared by chemical vapor deposition to the bottom electrode of a Ba0.25Sr0.75TiO3 capacitor and obtained good electrical characteristics.

Ultrathin SrTiO3 films prepared by chemical vapor deposition on Nb‐doped SrTiO3 substrates

The SrTiO3 ultrathin film capacitors were realized on Nb‐doped single‐crystal SrTiO3 substrates by chemical vapor deposition. The leakage current density of 10.4 nm thick SrTiO3 thin‐film capacitor was below 1×10−8 A/cm2 in the applied voltage range of −1.8 to +0.45 V, and its SiO2 equivalent thickness was 0.48 nm. The relative dielectric constant was over 160 for SrTiO3 thickness above 20 nm, but it decreased for SrTiO3 thickness below 20 nm. Dependence of leakage current on SrTiO3 film thickness was slight. These results could be explained by the existence of applied electric field concentration near the SrTiO3/electrode interface.

Chemical vapor deposition of (Ba,Sr)TiO3 thin films for application in gigabit scale dynamic random access memories

Abstract Our recent study respecting chemical vapor deposition of (Ba, Sr)TiO3 thin films was discussed focusing on conformal deposition technique and composition control. Perfect conformal (Ba, Sr)TiO3 films were deposited under the kinetically limited condition using Ba(THD)2-Sr(THD)2-TiO(THD)2 (THD is 2,2,6,6-tetramethyl-3,5-heptanedione) source system. We successfully fabricated three-dimensional capacitors using this conformal deposition technique. Under the kinetically limited condition, the Ba/Sr composition ratio was determined by the partial pressure ratio of Ba(THD)2 and Sr(THD)2. The self-matching of Ti/(Ba+Sr) stoichiometry occurred under a certain TiO(THD)2 supply range. It was proposed that the possible important reactant species were (THD)2Ba-O-Ti(THD)2 and (THD)2Sr-O-Ti(THD)2 dimers.

Composition Control of Barium Strontium Titanate Thin Films Prepared by Chemical Vapor Deposition

Composition control of barium strontium titanate thin films prepared by chemical vapor deposition using Ba(THD)2, Sr(THD)2, and Ti(THD)2(i-OC3H7)2 (THD: 2,2,6,6-tetramethyl-3,5-heptanedionate) has been studied by investigating the effects of deposition temperature and the supply rates of metal sources. Although there were complicated correlations among the deposition rates of Ba, Sr, and Ti under kinetically limited conditions, the deposition rate ratio of Ba/Sr was linearly related to the partial pressure ratio of Ba(THD)2/Sr(THD)2, and the ratio of Ti/(Ba+Sr) spontaneously approaches unity. In order to explain these characteristics, we proposed a model wherein the THD complex of Ba or Sr reacts with the THD complex of Ti and generates a dimer such as (THD)2Ba–O–Ti(THD)2, and this dimer becomes the dominant precursor for chemical vapor deposition (CVD) under kinetically limited conditions.

Control of Two Types of Dielectric Relaxation Current for Ta2O5 Metal-Insulator-Metal Capacitors

Ta2O5 is the most promising high-k dielectric candidate for metal-insulator-metal (MIM) capacitors, but its dielectric relaxation (DR) currents may cause irrecoverable charge loss, although DR is a universal phenomenon of normal dielectrics. Therefore, the Ta2O5 MIM capacitors DR chasracteristics and their control were investigated. Ta2O5 DR is composed of two components. One component shows t-1-type time decay, which is assumed to be caused by nonuniformity of electron polarization and is almost of the same order as that of SiN. Thus, its influence on dynamic random access memory (DRAM) operation will be limited. The other component shows t-0.5-type time decay, which is caused by hydrogen deoxidation of Ta2O5, and is dominant in the case of deoxidized Ta2O5 DR. It causes about 16% charge loss. Namely, it will have an adverse influence on DRAM operation. N2 annealing is a possible solution for the reduction of this t-0.5-type DR.

Low temperature (<500/spl deg/C) SrTiO/sub 3/ capacitor process technology for embedded DRAM

We have developed low temperature SrTiO/sub 3/ (ST) capacitor process for embedded DRAM. ST film deposited at 475/spl deg/C was crystallized without additional annealing. 0.53nm SiO/sub 2/ equivalent thickness (teq) ST capacitor with Ru electrodes was obtained. The leakage current of the concave structure capacitor was less than 1fA/cell at /spl plusmn/0.8V for 256K 3-dimensional (3D) capacitors fabricated by the low temperature ST process. ST capacitor process can satisfy demands on lower processing temperature and scalability to very thin dielectric layer with low leakage current.

In-situ gas cleaning technology of hot-wall batch-type reactor for (Ba,Sr)TiO/sub 3/

We present a novel approach to gas cleaning technology for Ba/sub x/Sr/sub (1-x)/TiO/sub 2/ (BST) residual coating in hot wall CVD reactors. It consists of two step continuous process. In the first step we use Cl/sub 2/ gas at 800 deg. C to remove Ba and Sr which have low vapor pressure. Second step consists of using ClF/sub 3/ gas to remove Ti at relatively low temperature. Vapor pressures of the chlorine compounds of Ba and Sr are considerably higher than those of their other existing compounds, thus by chlorination, Ba and Sr turn volatile and are easily etched off.

Hot-wall batch-type CVD tool for high-k (Ba,Sr)TiO/sub 3/ capacitors

A hot-wall batch type BST-CVD tool with fast thermal processing (FTP) furnace and individual vaporizing liquid source supply system (ILSS) was developed for uniform deposition of BST. We also employed an in-situ multi-step (IMS) process that is sequential repetition of thin amorphous BST deposition and its crystallization in the same reactor to reconcile conformal BST deposition and good electrical performances. BST deposited by our hot-wall CVD shows slight substrate dependence (metal coated or not), therefore hotwall CVD is superior to a single slice tool for reduction of test wafer running. IMS deposited BST shows almost 100% step coverage, lower carbon impurity concentration than single step deposited BST and sufficient electrical characteristics (leakage current <10/sup -7/ A/cm/sup 2/, Teq<0.5 nm) for both SRO and Ru electrodes.

Cylindrical Ru-SrTiO/sub 3/-Ru capacitor technology for 0.11 /spl mu/m generation DRAMs

We have developed a cylindrical Ru/ST/Ru capacitor for gigabit-scale DRAMs. Using cylindrical CVD-Ru as a storage node (SN), a new 2-step CVD-ST was employed to improve ST step coverage, surface morphology and to control composition at the Ru/ST interface. A SiO/sub 2/ equivalent thickness (t/sub eq/) of 0.6 nm and cell capacitance of 18 fF/cell with leakage current of 0.1 fA/cell at /spl plusmn/0.7 V applied voltage has been achieved on a 256K cylindrical Ru/ST/Ru capacitor array.

In-situ multi-step (IMS) CVD process of (Ba,Sr)TiO/sub 3/ using hot wall batch type reactor for DRAM capacitor dielectrics

We developed a new in-situ multi-step (IMS) process technology to achieve both conformal step coverage and high dielectric constant for CVD-BST. IMS is a sequential repetition of low temperature CVD of BST and its crystallization in a batch type hot wall reactor that enables uniform BST deposition over 200 mm wafers. Conformal growth of local epitaxially grown BST with a dielectric constant of more than 300 is attained by IMS combined with SrRuO/sub 3/ electrodes.