Katsuhiko Kurumada

Observation of Room Temperature Current Oscillation in InGaAs/InAlAs MQW Pin Diodes

Oscillatory behavior of current in the forward current-voltage characteristics for InGaAs/InAlAs multiple quantum well pin diodes was observed at room temperature for the first time. This oscillation became extremely clear at low temperature (80 K), and the oscillatory bias voltage region shrank with decreasing the well numbers.

N+ Self-Aligned MESFET for GaAs LSIs

The SAINT (Self-Aligned Implantation for N+-layer Technology) procers can embed n+- layers with very low resistance at a controlled distance from Schottky gate. It has been experimentally ascertained that the SAINT has feasibility for GaAs LSIs with advantages of gain, speed, uniformity and stability. An optimum n+-gate spacing in view of resistance-capacitance trade-off is found by combination of experiments and two-dimensional simulation. Guiding principles for the submicron gate are quantitatively discussed with results of the simulation.

A Large Barrier Height Schottky Contact between Amorphous Si-Ge-B and GaAs

Electrical properties of contacts between amorphous Si–Ge–B and GaAs are studied. A Schottky contact with a barrier height as large as 0.99 V has been realized. The barrier height can be varied by changing the composition of the amorphous films. Amorphous Si–Ge–B is applied to GaAs FETs as gate electrodes. A large saturated drain current of 900 µA/10 µm gate width has been realized. This value is 1.88 times as large as conventional normally-off GaAs MESFETs.

P-Column Gate Field Effect Transistor

Normally-off GaAs FETs with p-columns as the gate were fabricated. The transconductance exhibited considerably high value associated with relatively smaller sacrifice of the gate capacitance increase. The propagation delay of 145 ps/gate was observed from the ring oscillator made of 6 µm width devices with 2 µm column diameter dissipating 441 µW/gate.