Kavita Goswami

LVCMOS Based Thermal Aware Energy Efficient Vedic Multiplier Design on FPGA

In this work, we are integrating thermal aware design approach in energy efficient Vedic multiplier on FPGA. In the beginning of this universe, Veda describes heat receiving from the Sun god as Suryamrit (Surya i.e. Sun +Amrit i.e. Nectar= Suryamrit i.e. Nectar coming from the Sun God). Now, whole world is feeling anxious about temperature. How our thinking pattern is changing with evolution of mankind? This paper deals with that question and the whole work is going in direction to get solution of this problem with mechanism of ambient (room) temperature scaling and energy efficient LVCMOS I/O standard. LVCMOS is an acronym for low voltage complementary metal oxide semiconductor. In this Vedic multiplier, we are using three LVCMOS I/O standard. LVCMOS12 is available only in 65nm and 40nm FPGA. Rest LVCMOS18 and LVCMOS25 is available among 40nm, 65nm and 90nm FPGA. In order to test the thermal sustainability of our Vedic multiplier, we are testing it in three different room temperature 20°C, 30°C, and 40°C. Using LVCMOS25, there is 12.99%, 19.23% and 10.28% reduction in power dissipation on 90nm, 65nm and 40nm respectively. For LVCMOS25, when our Vedic multiplier design is migrated from 40nm design to 90nm design, there is 87.72% reduction in power dissipation of Vedic multiplier when temperature is constant 20°C.

Energy efficient vedic multiplier design using LVCMOS and HSTL IO standard

In this project, we are using LVCMOS and HSTL IO standards in order to match the resistance of input and output line, input and output port and Vedic multiplier. The primary purpose of Impedance matching is to eliminate transmission line reflection. Now, impedance matching is used to increase the stability of device with the help of IO standard. Therefore, selection of energy efficient IO standard will increase the energy efficiency of design under consideration. LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor) and HSTL (High Speed Transceiver Logic) are energy efficient IO standard. Energy efficient IO standards are used to decrease the power dissipation of Vedic multiplier. Then, we try to achieve more energy efficiency with different technology (40nm, 65nm, 90nm) based FPGA. There is 95.07%, and 63.7% leakage power reduction with HSTLII_D18 IO standard, when we migrate our design from Virtex-5 to Virtex-6, and Virtex-4 respectively. With the energy efficient LVCMOS18 IO standard, there is 94.64% 61.57% reduction in leakage power, when we migrate our design from Virtex-5 to Virtex-6 and Virtex-4.

Low Voltage Digitally Controlled Impedance Based Energy Efficient Vedic Multiplier Design on 28nm FPGA

Low Voltage Digitally Controlled Impedance (LVDCI) is an I/O standard available on FPGA. This design is LVDCI IO standard based Energy Efficient Vedic Multiplier Design on FPGA. Selection of IO standard play an important role in power dissipation of design. Therefore, we are going to select the most energy efficient IO standards in LVDCI family for Vedic Multiplier. This Vedic multiplier design is a part of project of Vedic arithmetic circuits. The final deliverable of this project is Vedic Processor by merging both concepts of Veda, first book of this world, and the latest technology of this world. In order to test thermal aware design, we want to see that how does an electronic device behave if we change the temperature of surrounding in which it is working. For that purpose we have taken temperatures of four different regions. Furnace Creek Ranch is area of North America recorded the highest temperature of the world that is 56.7°C [1]. Approximately, 53.5°C is the maximum temperature recorded in Mohenjo-Daro situated in Sindh Pakistan [1]. We have also taken median temperature of Delhi i.e. 40°C and standard normal temperature i.e. 21°C. We are operating Vedic Multiplier with the four different temperature and different LVDCI IO standard and observe device performance, and power dissipation. When we use 28nm FPGA under room temperature of 40°C, there are 93.42%, 92.6%, 93.99%, 93.59% and 89.79% reduction in total power dissipation of Vedic multiplier using LVDCI 15, LVDCI 18, LVDCI DV2 15, LVDCI DV2 18 and HSLVDCI 15 respectively. Similarly, when we use 28nm FPGA, there is approximately 90-96% reduction in leakage power dissipation of Vedic multiplier using different LVDCI and different temperature. There is no change in I/O power with change in temperature for uniform IO standard. When we use different IO standard of LVDCI family, there is significant reduction in leakage power. FPGA based on 28 nm technology is more energy efficient than 40 nm technology based FPGA.