Kavitha D. Buddharaju

Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. N-MOS devices thus fabricated with gate length ~150 nm showed excellent transistor characteristics with large drive current (1.0 times 103 muA/mum), high Ion/Ioff ratio (~107), good subthreshold slope (~80 mV/dec) and low drain-induced barrier lowering (~10 mV/V). Along with good electrical characteristics, the use of low cost bulk wafers, and simple gate definition process steps could make this device a suitable candidate for next generation technology nodes.

Highly sensitive measurements of PNA-DNA hybridization using oxide-etched silicon nanowire biosensors

The highly sensitive and sequence-specific detection of single-stranded oligonucleotides using nonoxidized silicon nanowires (SiNWs) is demonstrated. To maximize device sensitivity, the surface of the SiNWs was functionalized with a densely packed organic monolayer via hydrosilylation, subsequently immobilized with peptide nucleic acid (PNA) capable of recognizing the label-free complementary target DNA. Because of the selective functionalization of the SiNWs, binding competition between the nanowire and the underlying oxide is avoided. Transmission electron microscopy was conducted to clearly differentiate the SiNW surface before and after removal of SiO(2). Fluorescence microscopy was used to further realize the selectivity of the oxide-etched chemistry on the SiNWs and sequence specificity of PNA-DNA hybridization. The concentration-dependent resistance change measurements upon hybridization of PNA-DNA show that detection limit down to 10fM can be obtained. The SiNW devices also reveal the capability of an obvious discrimination against mismatched sequences. Among several efforts being made to improve detection sensitivity, this work addresses one significant issue regarding surface functionalization which enables highly sensitive biomolecular sensing with SiNWs.

Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications

Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.

DNA detection using nanostructured SERS substrates with Rhodamine B as Raman label

A technique is demonstrated to detect DNA hybridization at low concentrations, based on Surface-Enhanced Raman Scattering (SERS) using silicon nanostructures coated with gold-silver as substrate. Standard silicon process technologies were employed to fabricate the SERS substrates featuring nanogaps with a characteristic distance of 15+/-10nm. Target DNA was hybridized with cysteine-modified Peptide Nucleic Acids (PNA), which was previously fixed into the nanogaps as the capture sites. After hybridization, the introduced phosphate groups from the backbone of the target DNA showed strong affinity to an inorganic linker, Zr(4+), so that resulting in the assembly substrate-PNA-DNA-Zr. Since PNA does not possess phosphate groups, the linker is avoided when there is no hybridization from the complimentary DNA. Subsequently, the assembly of substrate-PNA-DNA-Zr was incubated with a Raman label, Rhodamine B (RB). The carboxylic acid group in RB reacted with the linker Zr(4+) allowing this Raman Label to be attached to the assembly substrate-PNA-DNA-Zr. The Raman peaks corresponding to RB were selected to detect the target DNA, with a detection limit of 1 x 10(-12)M.

CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach

This letter demonstrates, for the first time, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach. With matching of the drive currents of n- and p-MOSFETs using different gate lengths to achieve symmetric pull-up and pull-down, sharp ON- OFF transitions with high voltage gains (e.g., DeltaV OUT/DeltaV IN up to ~ 40 for V DD = 1.2 V) are obtained. The inverter maintains its good transfer characteristics and noise margins for wide range of V DD tested down to 0.4 V. Individual transistors show excellent subthreshold characteristics and drive currents. The results are discussed in light of the circuit performances reported for other advanced nonclassical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS-circuit functionality is thus demonstrated.

Chip-Level Thermoelectric Power Generators Based on High-Density Silicon Nanowire Array Prepared With Top-Down CMOS Technology

This letter, for the first time, reports a high-density silicon-nanowire (SiNW)-based thermoelectric generator (TEG) prepared by a top-down CMOS-compatible technique. The 5 mm × 5 mm TEG comprises of densely packed alternating n- and p-type SiNW bundles with each wire having a diameter of 80 nm and a height of 1 μm. Each bundle serving as an individual thermoelectric element, having 540 × 540 wires, was connected electrically in series and thermally in parallel. The fabricated TEG demonstrates thermoelectric power generation with an open circuit voltage (Voc) of 1.5 mV and a short circuit current (Isc) of 3.79 μA with an estimated temperature gradient across the device of 0.12 K.

Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach

We present, for the first time, the monolithic integration of Gate-Ail-Around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. The drive currents for N-and P-MOS transistors are matched using different number of channels for each to obtain symmetric pull-up and pull-down characteristics. Sharp ON-OFF transitions with high voltage gains (up to -45) are obtained which are best reported among the nanowire and carbon nanotube inverters. The inverters maintain their good transfer characteristics and noise margins for a wide range of VDD values, down to 0.2 V. Short circuit current at 0.2 V VDD is ~6 pA indicating excellent potential of these devices for low voltage and ultra low power applications. These results excel those reported in the literature for nanowire as well as FinFET (non-classical CMOS) inverters.

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

This paper reviews the progress of the vertical top-down nanowire technology platform developed to explore novel device architectures and integration schemes for green electronics and clean energy applications. Under electronics domain, besides having ultimate scaling potential, the vertical wire offers (1) CMOS circuits with much smaller foot print as compared to planar transistor at the same technology node, (2) a natural platform for tunneling FETs, and (3) a route to fabricate stacked nonvolatile memory cells. Under clean energy harvesting area, vertical wires could provide (1) cost reduction in photovoltaic energy conversion through enhanced light trapping and (2) a fully CMOS compatible thermoelectric engine converting waste-heat into electricity. In addition to progress review, we discuss the challenges and future prospects with vertical nanowires platform.

Improved Vertical Silicon Nanowire Based Thermoelectric Power Generator With Polyimide Filling

This letter demonstrates two-orders-of-magnitude enhancement in the performance of recently reported vertical silicon nanowire (SiNW)-based thermoelectric power generators (TEGs) by optimizing the filling material. As compared to SiO2 in the earlier work, the new device uses polyimide as filling material, which provides low parasitic thermal conduction and also reduces the damage to the nanowire tips. Consequently, an open-circuit voltage of 27.9 mV, a short-circuit current of 67 μA (both improved by ~ 17 ×), and a maximum power output of 0.47 μW (improved by ~ 313 ×) were obtained under a temperature difference of 70 K across the experimental setup. The reported improvements bring SiNW-TEGs a step closer to be used as a miniaturized clean energy source.

Highly sensitive sensors for alkali metal ions based on complementary- metal-oxide-semiconductor-compatible silicon nanowires

Highly sensitive sensors for alkali metal ions based on complementary-metal-oxide- semiconductor-compatible silicon nanowires (SiNWs) with crown ethers covalently immobilized on their surface are presented. A densely packed organic monolayer terminated with amine groups is introduced to the SiNW surface via hydrosilylation. Amine-modified crown ethers, acting as sensing elements, are then immobilized onto the SiNWs through a cross-linking reaction with the monolayer. The crown ether–functionalized SiNWs recognize Na+ and K+ according to their complexation ability to the crown ethers. The SiNW sensors are highly selective and capable of achieving an ultralow detection limit down to 50nM, over three orders of magnitude lower than that of conventional crown ether–based ion-selective electrodes.