Kazufumi Watanabe

A Technology for Reducing Flicker Noise for ULSI Applications

It is demonstrated that the formation of the atomic scale flattened Si/SiO2 interface is effective in reducing the Flicker noise in n-channel metal oxide semiconductor field effect transistors (n-MOSFETs). The atomic scale flattened Si/SiO2 interface is realized, the atomic scale flattened silicon surface is obtained by the HF/HCl wet-etching process, and then the silicon surface is oxidized by radicals generated in Kr/O2 mixed high-density microwave-excited plasma at 400°C. Applying these techniques, the trap density at the Si/SiO2 interface is markedly reduced since the surface roughness is minimized and Flicker noise is markedly reduced as compared with the conventional process.

Capacitance-Voltage measurement method for ultrathin gate dielectrics using LC resonance circuit

The capacitance-voltage (C-V) measurement method using the LC resonance circuit (LC resonance method) for ultrathin gate dielectrics having large leakage current is demonstrated. In the LC resonance method, only an external inductance and a resistance and a simple equivalent electrical circuit of MOS devices are employed. External inductance can be optimized using the equivalent quality factor. At each gate voltage bias point,parameters of MOS equivalent circuit are determined by fitting the calculation results to the measured impedance-frequency characteristics at the resonance frequency point. Total resistance value of MOS equivalent circuit that is determined from the dc gate current-gate voltage characteristics can be a good help in the fitting sequence. The rms error of calculated and measured impedance-frequency characteristics is used for the fitting verification. The sensitivity of rms error to the variation in MOS capacitance value is discussed to determine the accuracy of the LC resonance method. C-V measurements of both thick (EOT=7.0 nm) and thin (EOT=1.2/spl bsol/ nm) gate dielectrics are demonstrated and the electrical oxide thickness (EOT) values are extracted from the C-V characteristics. Comparison between the LC resonance method and the other C-V measurement methods is also made with respect to C-V measurement results to show the good applicability of the LC resonance method.

Examination of degradation mechanism due to negative bias temperature stress from a perspective of hole energy for accurate lifetime prediction

Abstract An evaluation method using the modified hole injection method is proposed to evaluate Negative Bias Temperature Instability (NBTI) in this paper. The physical backgrounds of the evaluation method are strictly discussed. The proposed method accelerates the degradation such as the threshold voltage ( V th ) shift by the amount of the hole injection without the high gate voltage stress. Our experimental and theoretical frameworks clarify that two degradation mechanisms, one follows the reaction–diffusion (R–D) model and another follows the hole trap/de-trap (HTD) model, coexist in NBTI. In the inversion layer, holes distributed in the quantized upper energy levels especially induce the degradation that follows the R–D model, and holes distributed in the ground energy level induce the degradation that follows the HTD model. Finally, the accurate NBTI lifetime prediction is demonstrated using the proposed acceleration method.

Circuit level prediction of device performance degradation due to negative bias temperature stress.

Abstract A circuit level methodology for predicting performance degradations due to negative bias temperature stress is developed in this paper. Degradation mechanism is discussed based on experimental observations. Then, models that consist of a threshold voltage shift and a drain current reduction are developed based on the degradation mechanism. The developed models are implemented into a compact MOSFET model so that we can directly link the local degradation of pMOSFETs’ electrical characteristics to the total circuit performances. The validity of the developed models is confirmed by the good agreement in simulated and measured results of I – V characteristics of pMOSFET in all the transistor working region before and after negative bias temperature stress. Then, circuit performance prediction is carried out for the stressed 199-stage ring oscillator on its waveform and oscillation frequency. Excellent agreements between the experimental results and predicted results are obtained.

Accurate circuit performance prediction model and lifetime prediction method of nbt stressed devices for highly reliable ulsi circuits

An accurate circuit performance prediction model and a device lifetime prediction method of negative bias temperature (NBT) stressed devices are proposed in this paper. The proposed model is constituted of a threshold voltage (Vth) shift and a drain current (ID ) reduction. The models can directly link the electrical characteristics degradation to the circuit simulation, thus enable us to design highly reliable ULSI circuits. The circuit performance prediction is confirmed by the experimental data of the oscillation frequency degradation and waveform variation of ring oscillator. The simulation results are in good agreement with the experimental results. Since only a suitable acceleration method allows us to develop the accurate models, the new negative bias temperature instability (NBTI) acceleration method using cold-holes is also developed. The very small saturation value of V th shift (<10mV) is observed. The detail of this physics is discussed in this paper. Finally, we demonstrate the accurate NBTI lifetime prediction using the new method

EOT measurement for ultra-thin gate dielectrics using LC resonance circuit [MOS devices]

The EOT measurement method, using the LC resonance circuit (LC resonance method), for thin gate dielectrics having a large leakage current, is demonstrated. In the LC resonance method, only an external inductance and a resistance and a simple equivalent electrical circuit of MOS devices are employed. The EOT value from thicker gate dielectrics (/spl sim/10 nm) to thinner gate dielectrics (/spl sim/1 nm) with large leakage current can be defined by the impedance-frequency characteristics at resonance and be verified at other frequency regions and with DC gate current-gate voltage characteristics.

A Large-Signal MOSFET Model Based on Transient Carrier Response for RF Circuits

Kazufumi Watanabe, Koji Kotani, Akinobu Teramoto, Shigetoshi, Sugawa and Tadahiro Ohmi Graduate School of Engineering, Tohoku University, New Industry Creation Hatchery Center, Tohoku University. Aza-Aoba 10, Aramaki, Aoba-ku, Sendai 980-8579, Japan, (Phone: +81-22-217-3977 / Fax: +81-22-217-3986). Email: k-watanabe@fff.niche.tohoku.ac.jp

Accurate Temperature Drift model of MOSFETs Mobility for Analog Circuits

An accurate compact MOSFETs model that can deal with effects of temperature drift is prerequisite for analog circuit design. Although the mobility behavior at high vertical field region is important for simulating analog circuits, however current physics based models neglect the temperature dependence of that at this region. In this paper, a new mobility model at high vertical field region is proposed. The developed model can capture the mobility behavior for different surface orientations, since this model is based on the essential physics. The model accuracy is verified by the experimental data.