Yukimasa Uchida

A 64Kb CMOS RAM

This report will cover the design of a fault-tolerant 8K×8b static RAM using a double polysilicon CMOS technology. Memory access is 70ns typically, while consuming 15mW operating power and 10μW standby power.

An 18 ns CMOS/SOS 4K static RAM

A high-speed CMOS/SOS 4K word/spl times/1 bit static RAM is described. The RAM features a MoSi/SUB 2/ gate CMOS/SOS technology with 2 /spl mu/m gate length and 500 /spl Aring/ thick gate oxide. Performance advantage of SOS over bulk is discussed for the scaled-down MOS LSI with 1-2 /spl mu/m gate. A standard 6-transistor CMOS cell and a two-stage sense amplifier scheme are utilized. In spite of the rather conservative 3.5 /spl mu/m design rule except for the 2 /spl mu/m gate length, the cell size of 36/spl times/36 /spl mu/m, the die size of 3.11/spl times/4.07 mm, and the typical read access and cycle time of 18 ns are achieved. The active and standby power dissipation are 200 mW and 50 /spl mu/W, respectively.

A low power resistive load 64 kbit CMOS RAM

A fully asynchronous 8K word/spl times/8 bit CMOS static RAM with high resistive load cells is described. For fabricating the RAM, an advanced double polysilicon 2 /spl mu/m CMOS technology has been developed. Internally clocked dynamic peripheral circuits with address transition detectors are implemented to achieve high speed and low power simultaneously. A new CMOS fault-tolerant circuit technology is also introduced for improving fabrication yield without sacrificing operating speed or standby power. The resulting cell size and die size are 15/spl times/19 /spl mu/m and 4.87/spl times/7.22 mm, respectively. The RAM offers, typically, 70 ns access time, 15 mW operating power, and 10 /spl mu/W standby power.

A 1024-bit MNOS RAM using avalanche-tunnel injection

MNOS memory cells which consist of one MNOS transistor and two MOS transistors are incorporated into a fully decoded 1024-word by 1-bit random access memory (RAM) with nonvolatility. The features of the present nonvolatile RAM are: 1) by introducing a novel mode of write operation, electrical isolators, such as p-n junction isolation between the memory cells and the other circuits are not required, 2) stored data can last more than one year without any kind of external power supply, 3) the chip size of the memory is 3.60/spl times/3.61 mm/SUP 2/, 4) the read-access time is 600 ns and the write cycle time is 10 /spl mu/s-100 /spl mu/s.

Floating substrate effects in SOS VLSIs

New floating substrate effects which degrade the operating speed of scaled down SOS MOS VLSIs are investigated, utilizing CMOS/SOS ring oscillators with substrate electrodes and CMOS/SOS RAMs. Reverse bias floating substrate effect due to charge pumping, which increases the propagation delay time, is more pronounced with increasing substrate impurity concentration and/or decreasing power supply voltage. This charge pumping rate is greater in PMOS than in NMOS. CMOS/SOS RAM access time degradation is caused from the noise current in deselected transfer gate transistors, due to forward bias floating substrate effect which comes from the capacitive coupling between the bit line and the substrates of deselected transfer gate transistors. The importance of introducing device structures, which fix transistor substrate potential in high-speed SOS VLSI designs, is discussed based on the above results.

N-Channel High Speed Nonvolatile Static RAM Utilizing MNOS Capasitors

An improved n-channel nonvolatile static RAM is proposed by introducing a new memory cell which consists of a pair of MNOS capacitors and a 6-transistor MOS flipflop circuit. The RAM can be operated as a high speed static memory under a stable power supply, and as a nonvolatile memory by externally applying erasing/writing signals to a common MNOS gate signal line. Self-generation of inhibiting voltage by bootstrapping effect of MNOS capacitors enables this memory to operate with a single power supply of 5 V. Fully decoded 16-bit experimental devices are fabricated and evaluated. This technology shows the possibility to realize a high packing density memory of 4 K-bit or beyond with the access time of less than 100 ns using 3 µm design rule.

1 K-bit nonvolatile semiconductor read/write RAM

A 1024-bit nonvolatile semiconductor read/write random access memory (RAM) is described which is operated as a static RAM under a stable power supply, and the stored information can be transferred into MNOS memory transistors for nonvolatile storage when the power supply is turned off. A nonvolatile flip-flop cell consisting of 8 MOS transistors and 2 MNOS transistors is used on the basis of p-channel silicon gate technology. The chip size is 4.36 × 5.50 mm2. Typical read access time is 900 ns, and the stored data can last for more than one year. Endurable power on and off cycles are 105cycles.

High Speed MoSi2-Gate CMOS/SOS Devices

Characterization and optimization of CMOS/SOS devices with the effective channel length of 1.5 µm utilizing MoSi2-gate technology are investigated from the viewpoint of practical realization of CMOS/SOS VLSIs. Double ion implantation into the channel region was found to be effective for suppressing leakage currents in shorter channel CMOS/SOS devices. Floating substrate effect due to charge pumping was also studied. Using the MoSi2-gate CMOS/SOS technology, feasibility for a 4K (4K×1)-bit static RAM was verified.

N-Channel MNOS EAROM for TV Electronic Tuning System

A new n-channel MNOS technology for EAROM applications has been developed by introducing a threshold voltage control technique. The technology is principally based on a low energy implantation of boron ions for obtaining a positive center voltage in the threshold window, which results in better retentivity. By incorporating this MNOS technology and n-well CMOS technology on an isolated epitaxial layer, an n-channel MNOS EAROM is fabricated for TV electronic tuning system. The EAROM utilizes the two MNOS transistors per cell configuration. The device showed a long data retention time over 10 years at 80 °C after 105 erasing/writing cycles, therefore the technology appears to be quite promising for EAROM applications.

A 256 bit Nonvolatile Static Random Access Memory with MNOS Memory Transistors

A p-channel 256 bit nonvolatile static RAM which is essentially free from any limitation to the memory cycles is developed by means of a new concept of a nonvolatile flip-flop. The logical organization is 64 word × 4 bit. The memory can be operated as a static memory with access time of 400 ns and cycle time of 1 µs under a stable power supply, and as a non-volatile memory with data retentivity of about one year. Nonvolatile writing to the MNOS transistors is done only when the power supply is turned off and on. The allowable number of on/off cycles can exceed 105 cycles under normal operating conditions. Power dissipation as a static RAM is less than 600 mW and that as a nonvolatile memory is zero. Both inputs and outputs are TTL compatible except for the signal to the gate of MNOS transistors.