Tomoko Mizutani

Analysis and prospect of local variability of drain current in scaled MOSFETs by a new decomposition method

Causes of drain current local variability are analyzed by decomposing into current variability components. Besides VTH and Gm components, it is newly found that effects of “current onset” variability caused by channel potential fluctuations largely contribute to the current variability and that Gm component is relatively small in the saturation region. It is shown that both VTH and current onset components decreases with reducing channel dopants, indicating that intrinsic channel is very effective to reduce current variability.

Measuring threshold voltage variability of 10G transistors

Threshold voltage (V<inf>TH</inf>) variability of 10G (10 billion) transistors is measured using a special device-matrix-array test-element-group (DMA TEG) exclusively for ultra-fast V<inf>TH</inf> measurements. It is found that V<inf>TH</inf> variability in nFETs almost follows the normal distribution up to ±6σ, while pFETs have a clear “tail” in low V<inf>TH</inf> region. The origin of the non-normal distribution is analyzed by measuring transistors fabricated in two different fabs and by 3D device simulation.

Suppression of DIBL and current-onset voltage variability in intrinsic channel fully depleted SOI MOSFETs

Intrinsic channel SOI MOSFETs were fabricated and their variability were compared with conventional bulk MOSFETs. It is found for the first time that, besides VTH variability, both DIBL variabitlity and current-onset voltage variability are well suppressed in the intrinsic channel SOI MOSFETs thanks to non-intentionally doped channel. Reduction of channel doping is essential to reduce the characteristics variability in scaled FETs.

Origin of Larger Drain Current Variability in N-Type Field-Effect Transistors Analyzed by Variability Decomposition Method

The origin of larger on-state drain current (ION) variability in n-type field-effect transistors (NFETs) than that in p-type field-effect transistors (PFETs), is investigated by evaluating FETs fabricated using 65 nm technology. It is found that the larger ION variability in NFETs is caused by not only the larger threshold voltage component but also the larger current-onset voltage component of the ION variability in NFETs. Moreover, it is experimentally confirmed that ION variability of NFETs can be reduced by the halo carbon co-implantation through the reduction of threshold voltage and current-onset voltage components of the ION variability in NFETs.

Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

We demonstrated Silicon on Thin Buried oxide (SOTB) CMOS especially designed for ultralow-voltage (ULV) operation down to 0.4 V for the first time. Utilizing i) dual-poly gate stack with high-k having quarter-gap work functions best for the ULV CMOS operation, and ii) a novel “local ground plane (LGP)” structure that significantly improves short-channel effect (Vth roll off) without increasing local variability unlike halo for bulk, low-leakage SRAM operation was demonstrated with adaptive-body-bias (ABB) scheme.

High-Temperature Properties of Drain Current Variability in Scaled Field-Effect Transistors Analyzed by Decomposition Method

The properties of drain current variability in field-effect transistors (FETs) at high temperature are experimentally investigated. It is found that the on-state drain current (ION) at high temperature has a strong correlation with ION at room temperature and that there is no anomalous ION change from room temperature to high temperature. It is also found that ION variability at high temperature is smaller than that at room temperature. The origin of the decrease in ION variability with increasing temperature is analyzed by the decomposition method developed in our previous work. It is clarified that the decrease in the current–onset voltage component plays a dominant role, especially in the saturation region. Moreover, it is also clarified that thermal excitation of carriers suppresses current–onset voltage variability, and ultimately the current–onset voltage component of ION variability with increasing temperature.

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, we describe our recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other logic circuits. Our 32-bit RISC CPU chip, named “Perpetuum Mobile,” has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.

Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs

Drain current variability in silicon-on-thin-BOX (SOTB) MOSFETs are analyzed by decomposing into current variability components and compared with conventional bulk MOSFETs. It is found that drain current variability in SOTB MOSFETs is largely suppressed thanks to not only reduced VTH variability but also reduced current-onset voltage (COV) variability due to intrinsic channel.

Analysis of transistor characteristics in distribution tails beyond ±5.4σ of 11 billion transistors

Transistors in distribution tails of 11G (11 billion) transistors were intensively measured and compared with transistors in the center of distribution. It is found that, while VTH defined by subthreshold constant current (VTHC) deviates from the normal distribution, extrapolated VTH (VTHEX) roughly follows the normal distribution. It is also found that some transistors show extraordinary low on-current (ION) which deviates from the normal distribution. The origin of abnormal distribution and the impact on yield loss are discussed based on measured results and 3D device simulation.

Origin of “current-onset voltage” variability in scaled MOSFETs

Present work analyzes the cause of “current-onset voltage” variability, which has been newly found to largely affect drain current variability [1]. It is found by 3D device simulation that the “current-onset voltage” variability is determined by how largely the channel potential fluctuates by random dopant disposition. Reducing RDF will suppress both threshold voltage and current-onset voltage variability as well.