Kazuya Fukuhara

Overlay improvement in nanoimprint lithography for 1×-nm patterning

Nanoimprint lithography (NIL) is becoming a promising technique for fine-patterning with a lower cost than other lithography techniques. High overlay accuracy is one of the issues in NIL. Using die-by-die alignment with moire fringe detection, an NIL alignment measurement accuracy below 1 nm and an overlay accuracy below 5 nm have been reported. On the other hand, the requirement for overlay in 2020 is estimated to be 3–4 nm for dynamic random access memory, flash and logic devices. In order to make the overlay accuracy requirement qualify from the semiconductor industry, a lot of technology enhancements, such as the improvement of overlay control accuracy for NIL-tools, image placement accuracy improvement for NIL templates, mix and match technique of NIL, and other lithography tools such as immersion exposure ones, are needed. In this paper, the authors describe the evaluation of the NIL overlay performance using up-to-date NIL tools, and discuss the potentials of NIL overlay in the future. Alignment ac...

Solutions with precise prediction for thermal aberration error in low-k1 immersion lithography

Thermal aberration becomes a serious problem in the production of semiconductors for which low-k1 immersion lithography with a strong off-axis illumination, such as dipole setting, is used. The illumination setting localizes energy of the light in the projection lens, bringing about localized temperature rise. The temperature change varies lens refractive index and thus generates aberrations. The phenomenon is called thermal aberration. For realizing manufacturability of fine patterns with high productivity, thermal aberration control is important. Since heating areas in the projection lens are determined by source shape and distribution of diffracted light by a mask, the diffracted pupilgram convolving illumination source shape with diffraction distribution can be calculated using mask layout data for the thermal aberration prediction. Thermal aberration is calculated as a function of accumulated irradiation power. We have evaluated the thermal aberration computational prediction and control technology “Thermal Aberration Optimizer” (ThAO) on a Nikon immersion system. The thermal aberration prediction consists of two steps. The first step is prediction of the diffraction map on the projection pupil. The second step is computing thermal aberration from the diffraction map using a lens thermal model and an aberration correction function. We performed a verification test for ThAO using a mask of 1x-nm memory and strong off-axis illumination. We clarified the current performance of thermal aberration prediction, and also confirmed that the impacts of thermal aberration of NSR-S621D on CD and overlay for our 1x-nm memory pattern are very small. Accurate thermal aberration prediction with ThAO will enable thermal aberration risk-free lithography for semiconductor chip production.

Study of nanoimprint lithography (NIL) for HVM of memory devices

A low cost alternative lithographic technology is desired to meet the decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the candidates for alternative lithographic technologies.[1][2][3] NIL has such advantages as good resolution, critical dimension (CD) uniformity and low line edge roughness (LER). On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the HVM, it is necessary to overcome these three challenges simultaneously.[4]-[12] In our previous study, we have reported a dramatic improvement in NIL process defectivity on a pilot line tool, FPA-1100 NZ2. We have described that the NIL process for 2x nm half pitch is getting closer to the target of HVM.[12] In this study, we report the recent evaluation of the NIL process performance to judge the applicability of NIL to memory device fabrications. In detail, the CD uniformity and LER are found to be less than 2nm. The overlay accuracy of the test device is less than 7nm. A defectivity level of below 1pcs./cm2 has been achieved at a throughput of 15 wafers per hour.

Improvement of nano-imprint lithography performance for device fabrication

A low cost alternative lithographic technology is desired to cope with the challenges in decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the viable candidates.[1][2][3] NIL has been a promising solution to overcome the cost issue associated with expensive process and tool of multi patterning and EUVL. NIL is a simple technology and is capable of forming critical patterns easily. On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the High Volume Manufacturing (HVM), it is necessary to overcome these three challenges simultaneously.[4]-[10] In our previous study, we have reported improvement in NIL overlay, defectivity and throughput by the optimization of resist process on a pilot line tool, FPA-1200 NZ2C. In this study, we report recent evaluation of the NIL performance to judge its applicability in semiconductor device HVM. We have described that the NIL is getting closer to the target of HVM for 2x nm half pitch.[8]Defectivity level below 1pcs/cm2 has been achieved for the 2x nm half pitch L/S. The overlay accuracy of the test device is being improved down to 6nm or lower by introducing high order distortion correction.

Improvement of CD-SEM mark position measurement accuracy

CD-SEM is now attracting attention as a tool that can accurately measure positional error of device patterns. However, the measurement accuracy can get worse due to pattern asymmetry as in the case of image based overlay (IBO) and diffraction based overlay (DBO). For IBO and DBO, a way of correcting the inaccuracy arising from measurement patterns was suggested. For CD-SEM, although a way of correcting CD bias was proposed, it has not been argued how to correct the inaccuracy arising from pattern asymmetry using CD-SEM. In this study we will propose how to quantify and correct the measurement inaccuracy affected by pattern asymmetry.