Koichi Yako

Electron holography for analysis of deep submicron devices: Present status and challenges

A potential distribution analysis of source/drain (SD) regions in sub-30-nm-gate-length metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented as an example of the present status of electron holography analysis. First, the authors describe experimental setups that determine the resolutions of the analysis in practice. They show that specimen preparation artifacts significantly affect the energy resolution and that the artifacts can be reduced by preparing specimens using low-energy back side ion milling. Second, they describe the SD potential analysis in sub-30-nm-gate-length MOSFETs.

In-situ electron holography of surface potential response to gate voltage application in a sub-30-nm gate-length metal-oxide-semiconductor field-effect transistor

The response of the electrostatic potential distribution within a metal-oxide-semiconductor field-effect transistor (MOSFET) to an external electric field was revealed using electron holography cross-sectional in-situ observation while applying the gate voltage to a transistor scaled down to a 25-nm gate length. Charging effects due to electron irradiation were taken into account by using complementary numerical device simulation. Direct observation of the channel potential and its response to the gate voltage can be used to determine the gate electrode effective work-function for scaled MOSFETs.

Aggressive design of millisecond annealing junctions for near-scaling-limit bulk CMOS using raised source/drain extensions

An aggressive junction design concept is proposed for further scaling of bulk CMOS featuring selective epi-growth raised source/drain extentions (RSDext) in conjunction with high temperature millisecond annealing (MSA) process. The junction design window enlarged by introducing the RSDext enables us to perform elaborate control of slight ldquointentionalrdquo diffusion onto the MSA process rather than aiming complete--diffusion-less junctions. Such the ldquoeffectiverdquo ultra-shallow junctions under the raised S/D-extentions are demonstrated, in this paper, to exhibit both lower parasitic resistance and lower junction leakage while maintaining superior short-channel-effect suppression, i.e. VTH roll-off characteristics, and any reliability issues.

Cold (−100°C) carbon co-implantation into high phosphorus doping source/drain extensions for aggressively scaled NFETs

A −100°C carbon co-implantation into phosphorus-doped source/drain extensions has been developed, providing for low junction leakage. NFETs made using cold carbon co-implantation and ultra-low energy phosphorus ion implantation showed high activation (Rs∼ 500 ohm/sq) and sub-20 nm depth abrupt N+ junction.

Direct two-dimensional electrostatic potential cross-sectional mapping of sub-30-nm MOSFET under operation mode using electron holography

Electron holography (EH) cross-sectional observations were used to delineate terminal-voltage induced changes in an electrostatic potential distribution in a MOSFET under operating conditions. Gate and drain voltages were applied to a 25-nm-gate-length MOSFET during EH observations to investigate how the terminal-voltage application changed the potential. Combined with a precise device simulation, this EH observation enables us to understand short-channel device behavior, such as drain-induced barrier-height lowering, under actual operation conditions that lead to more comprehensive and reliable device design.

Parasitic resistance and leakage reduction by raised source / drain extention fabricated with cluster ion implantation and millisecond annealing

We designed and fabricated sub-30 nm gate length pMOSFETs developing the raised source/drain extension (RSDext) process. Our process features usages of cluster-ion (B18H22) implantation and high-temperature millisecond annealing processes and a facet-structure-control of the RSDext of less than 10 nm thickness for suppressing a fringe capacitance increase for the “effective” ultra-shallower junction formation. As the results, experimentally obtained our pMOSFETs with raised source/drain extension show almost the same LMIN, 1/2 times lower parasitic resistance and lower junction leakage.