Kazuyoshi Arai

Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects

High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7- µm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described. Properties examined include Kelvin and stack chain resistances of Cu interconnects as well as Ion-Ioff, threshold voltage shift, and junction leakage of transistors. It was found that the electrical properties were not affected by bonding, thinning and debonding process indicating good feasibility of 3D stacking integration to the strain and low-k technology.

A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW applications

An ultra-thinning down to 2.6-μm with and without Cu contamination at 1013 atoms/cm2 using 300-mm wafer proven by 2Gb DRAM has been developed for the first time. The impact of Si thickness and Cu contamination at wafer backside for DRAM yield including retention characteristics is described. Thickness uniformity for all wafers after thinning was below 2-μm within 300-mm wafer. A degradation in terms of retention characteristics occurred after thinning down to 2.6-μm while no degradation after thinning down to 5.6-μm for both wafer and package level test were found.

Influence of wafer thinning process on backside damage in 3D integration

Ultra-thinning less than 10 microns of Si wafer is expected to realize small TSV feature which provides low aspect ratio and coupling capacitance. However, a detail of residual surface damage during thinning is unrevealed. In this paper, subsurface damage following wafer thinning from the back of 300 mm wafers using three different types of thinning process was investigated by means of Raman spectroscopy, XTEM, and Positron annihilation analysis, respectively. A coarse grinding generates significant rough subsurface ranged several micron and damage layer including amorphous and plastic-deformed Si along grinding topography. Fine grinding, second step of thinning, reduced those surface roughness and almost removed after thinning at least removal of 50 microns. However, plastic-deformed subsurface layer with a thickness of 100 to 200 nm are still remained which leaves an inside elastic stress layer ranging up to about 10 microns in depth. Chemical-Mechanical Polishing (CMP) process as a final step of thinning enables to remove residual damages such as structural defects and lattice strains after 1-5 microns thick polishing while vacancy-type defects only remain.