Nobuhide Maeda

Development of sub 10-µm ultra-thinning technology using device wafers for 3D manufacturing of terabit memory

200-mm and 300-mm device wafers were successfully thinned down to less than 10-µm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50-nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9-µm, switching charge showed no change by the thinning process. CMOS logic device wafers thinned to 7-µm indicated neither change in Ion current nor junction leakage current. Thinning such wafers to <10-µm will allow for lower aspect ratio less than 4 of Through-Silicon-Via (TSV) in a via-last process.

Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects

Influence of the sidewall roughness in through-silicon via (TSV) on leakage currents has been studied. Micro steps along the sidewall, so-called scalloping, formed by Bosch etching, are strongly related to leakage currents between adjacent TSVs. Microcracks in the SiON barriers were observed by TEM analysis and correlated with the sidewall roughness. FEM simulations of the stress concentration along the sidewall roughness clarified the origin of cracking. A non-Bosch etching process showed smooth sidewall surface and we consider it to be feasible for reliable TSV interconnects.

Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects

High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7- µm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described. Properties examined include Kelvin and stack chain resistances of Cu interconnects as well as Ion-Ioff, threshold voltage shift, and junction leakage of transistors. It was found that the electrical properties were not affected by bonding, thinning and debonding process indicating good feasibility of 3D stacking integration to the strain and low-k technology.

Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology

Diffusion behavior of Cu in Cu through-silicon-vias (TSVs) fabricated using low-temperature plasma enhanced chemical vapor deposition (LT-PECVD) has been evaluated. Silicon oxynitride (SiON) barrier films were formed by LT-PECVD at 150 °C. Cu diffusion rate was found to increase with decreasing film density. The critical density and thickness for prevention of Cu diffusion into Si substrate have been estimated. In case of a film with density >60% of the bulk value and/or thickness >100 nm, no change of electrical resistance for stacked wafers containing TSVs was observed after 1000 cycles of thermal stress. According to above results, SiON film formed at 150 °C can be used for the TSV process without any degradation of electrical characteristics and reliability, enabling a reduction in total process temperature in the wafer-on-wafer technology.

Stress sensitivity analysis on TSV structure of wafer-on-a-wafer (WOW) by the finite element method (FEM)

In the trough silicon via (TSV) structure for 3-dimentional integration (3DI), large thermal-mechanical stress acts in the BEOL layer caused by the mismatch in thermal expansion coefficient (CTE) of the TSV materials. The resulting high-stress region is thought to be the critical point for the initiation of the cracking or the de-lamination that affects the mechanical reliability. In this study, the stress of multi-stacked thin Si wafers composed of copper TSV and copper/low-k BEOL structure was analyzed by the finite element method (FEM), aiming to reduce the stress of LSI devices of 3D-IC. The results of sensitivity analysis using design of experiment (DOE) indicated that the thickness of the adhesive layer is the key factor for the structural integration of TSV design. It is suggested that the wafer-on-a-wafer (WOW) process has reliability about 1.5 to 1.75 times higher in the TSV structure with BEOL interconnects.

TSV (through silicon via) interconnection on wafer-on-a-wafer (WOW) with MEMS technology

The fabrication of WOW (wafer-on-a-wafer) with MEMS technology has been developed. A wafer was thinned and stacked on a base wafer. After the TSVs were patterned on the thinned wafer, they were filled by Cu for interconnection. The wafers were bonded with benzocylcobutene (BCB, CYCLOTENETM) as an adhesive material. The BCB layer was also acted as a dielectric layer between top and bottom silicon wafers. The TSVs were created by DRIE (Deep Reactive Ion Etching) and filled by Cu electroplating. This paper describes that thinned Si wafers down to 20µm were stacked on a base wafer with TSVs interconnection filled by Cu. The thinned wafers were stacked up to seven. The electrical characteristics were measured by daisy-pattern including 243 TSVs filled by Cu and the stress simulation for TSV was also shown.

Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications

An ultra-thinning down to 4-μm using 300-mm wafer proven by 40-nm Node 2Gb DRAM has been developed for the first time. Three different types of thinning process including coarse grinding, fine grinding, and stress relief were optimized and an atomic level vacancy less than 10-nm in depth at backside of wafer was formed successively. Thickness uniformity even after thinning down to 4-μm was approximately 1-μm within 300-mm wafer. No degradation in terms of retention characteristics and distribution employing 2Gb DRAM wafer was found after ultra-thinning. This suggests that no damage occurred due to thinning processes including wafer bonding and debonding steps. These results indicate good feasibility for multi-stack Wafer-on-Wafer (WOW) processes with the lowest aspect ratio of TSVs and parasitic capacitance, and enable multi-stacking for Tera-scale high density memory.

A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW applications

An ultra-thinning down to 2.6-μm with and without Cu contamination at 1013 atoms/cm2 using 300-mm wafer proven by 2Gb DRAM has been developed for the first time. The impact of Si thickness and Cu contamination at wafer backside for DRAM yield including retention characteristics is described. Thickness uniformity for all wafers after thinning was below 2-μm within 300-mm wafer. A degradation in terms of retention characteristics occurred after thinning down to 2.6-μm while no degradation after thinning down to 5.6-μm for both wafer and package level test were found.

Development of low temperature dielectrics down to 150°C for multiple TSVs structure with Wafer-on-Wafer (WOW) technology

With evaluation of various dense silicon-oxy-nitride (SiON) films, a critical density and thickness against to Cu diffusion into Si substrate has been evaluated. Density of SiON films varied with deposition temperature using Plasma-Enhanced Chemical-Vapor-Deposition (PECVD) was ranged from 56% to 69% for bulk film. Cu diffusion increased with decreasing the film density, resulting in 3.5 × 1010 cm2/s at 63% density. In case of 100-nm thick of SiON film with 63% density formed at 150°C, leakage current and breakdown voltage were <1 × 108 A/cm2 and >4.5 MV/cm, respectively. There is no change of electrical resistance after 1000 cycles of thermal stress for stacked wafers with multiple Through-Silicon-Vias (TSVs). Therefore, the SiON formed at 150°C enables as barrier layer providing enough reliability for TSV interconnects in the Wafer-on-Wafer (WOW) technology.

Impact of Thermomechanical Stresses on Bumpless Chip in Stacked Wafer Structure

Crack formation due to thermomechanical stresses generated by a dielectric polymer thicker than 20 µm and by that with high modulus during the bumpless chip-on-wafer (COW) process has been investigated. According to the stress simulation, thermal stresses increase with polymer thickness where the stress value ranges from 100 to 200 MPa for benzocyclobutene (BCB)-based resin. Thermal stresses in the hybrid structure using epoxy-based resin and BCB-based resin were calculated to be less than 100 MPa. Thus, the reduction of the thicknesses of the polymer as well as the Si chip was found to be effective in avoiding crack formation in the COW structure. Moreover, to investigate the crack driving force, the energy release rate (ERR) was calculated. The crack propagates toward the Si chip corner and the result is consistent with the experiment. On the COW structure, a thin Si chip and a low-modulus polymer expand the process window.