S. Kodama

Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications

An ultra-thinning down to 4-μm using 300-mm wafer proven by 40-nm Node 2Gb DRAM has been developed for the first time. Three different types of thinning process including coarse grinding, fine grinding, and stress relief were optimized and an atomic level vacancy less than 10-nm in depth at backside of wafer was formed successively. Thickness uniformity even after thinning down to 4-μm was approximately 1-μm within 300-mm wafer. No degradation in terms of retention characteristics and distribution employing 2Gb DRAM wafer was found after ultra-thinning. This suggests that no damage occurred due to thinning processes including wafer bonding and debonding steps. These results indicate good feasibility for multi-stack Wafer-on-Wafer (WOW) processes with the lowest aspect ratio of TSVs and parasitic capacitance, and enable multi-stacking for Tera-scale high density memory.

A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW applications

An ultra-thinning down to 2.6-μm with and without Cu contamination at 1013 atoms/cm2 using 300-mm wafer proven by 2Gb DRAM has been developed for the first time. The impact of Si thickness and Cu contamination at wafer backside for DRAM yield including retention characteristics is described. Thickness uniformity for all wafers after thinning was below 2-μm within 300-mm wafer. A degradation in terms of retention characteristics occurred after thinning down to 2.6-μm while no degradation after thinning down to 5.6-μm for both wafer and package level test were found.

Impact of Thermomechanical Stresses on Bumpless Chip in Stacked Wafer Structure

Crack formation due to thermomechanical stresses generated by a dielectric polymer thicker than 20 µm and by that with high modulus during the bumpless chip-on-wafer (COW) process has been investigated. According to the stress simulation, thermal stresses increase with polymer thickness where the stress value ranges from 100 to 200 MPa for benzocyclobutene (BCB)-based resin. Thermal stresses in the hybrid structure using epoxy-based resin and BCB-based resin were calculated to be less than 100 MPa. Thus, the reduction of the thicknesses of the polymer as well as the Si chip was found to be effective in avoiding crack formation in the COW structure. Moreover, to investigate the crack driving force, the energy release rate (ERR) was calculated. The crack propagates toward the Si chip corner and the result is consistent with the experiment. On the COW structure, a thin Si chip and a low-modulus polymer expand the process window.

Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation

The prospects of three-dimensional (3D) integration for Terabyte large scale integration using bumpless interconnects with low-aspect-ratio TSVs and ultra-thinning are discussed. Bumpless (no bump) interconnects between wafers are a second-generation alternative to the use of microbumps for Wafer-on-Wafer (WOW) technology. Ultra-thinning of wafers down to 4 μm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of ThroughSilicon-Vias (TSVs). Our bumpless interconnects technology is classified into Via-Last, which is performed from the front side after thinning, and stacking Back-to-Front, in which any number of thinned 300mm wafers and/or heterogeneous dies can be integrated. From an economic point of view, in many situations WOW is the leading 3D process because stacking at the wafer level drastically increases the processing throughput, and using multi-level bumpless interconnects, with individual wiring die-to-die, provides an appropriate yield that is equivalent to or greater than that achievable with 2D processes when scaling down to 22 nm nodes and beyond.

Development of ultra-thin Chip-on-Wafer process using bumpless interconnects for three-dimensional memory/logic applications

Chip-on-Wafer (COW) stacking structure using stack-first and bumpless interconnects was successfully fabricated for the first time. Chips were arrayed and bonded onto the wafer by back-to-face and gap filling between chips were carried out using organic material without void formation. Chips on the wafer were thinned down to 5 μm. Via-holes were formed at off-chip area (outside the chip). Copper redistribution line was formed using the via-first Damascene method. Lower leakage current as low as back ground was found between pads. No failure and an approximate 100% yield were achieved in the vertical wiring for multi-chips COW stacking.

Development of cost-effective wafer level process for 3D-integration with bump-less TSV interconnects

The multi-stack processes for wafer-on-wafer (WOW) have been developed. The key features are bumpless interconnects adapted to TSVs and extendibility for chip-on-wafer (COW) taking high throughput into account. In order to realize the multi-stacked wafers with ultra thinned wafer of less than 10μm with an adhesive polymer, several processes have been optimized. The thickness of the wafer after back-grinding was controlled within the total thickness variation (TTV) of 1.2μm on wafer-level of 8 inch. As the dielectric film for the side wall of though silicon vias (TSV), SiN film with low deposition temperature of 150 °C has been developed and applied for TSV process without degradation for electrical characteristics. The uniformity of Cu electro-plating has been improved that the overburdened Cu from the surface was decreased from 13.3 μm to 0.7 μm by optimizing plating solution. The CMP process following Cu electro-plating has been customized for the high rate of 5 μm/min. Finally, the stacked wafer has been evaluated for thermal cycle test (TCT) of 100 cycles with -65 to 150 °C. The result showed that there was no degradation for reliability and packaging process.

Electrical characteristics of bumpless interconnects for through silicon via (TSV) and Wafer-On-Wafer (WOW) integration

This paper describes electrical characteristics of bumpless and dual-damascene TSV interconnects for three-dimensional integration (3DI) using Wafer-on-Wafer (WOW) technology. Process optimization counter to integration issues of TSV formation process is demonstrated using test vehicle fabricated with 300-mm wafer and characterized by chain resistance and leakage current in the wafer level.

Impact of Thermomechanical Stresses on Ultra-thin Si Stacked Structure

Three-dimensional integration (3DI) with through-silicon vias (TSVs) can reduce interconnect delay, form factor, and power consumption, offering the advantage of enhanced system performance compared with two-dimensional integration. TSV density with a low aspect ratio is the key to realizing high-density memory and high bandwidth. In our previous studies, we developed a wafer-on-wafer (WOW) 3DI technology featuring thinning-first before bonding, TSV-last without bumps (bumpless), and Cu TSV interconnects. Using a 40 nm-node 2-Gb DRAM wafer, ultra-thinning down to a wafer thickness of 4 μm has been successfully demonstrated without any degradation of the device characteristics. In this study, the impact of thermomechanical stresses on an ultra-thin Si stacked structure was investigated using two-dimensional finite element analysis (2D-FEA). Model structures with different Si thicknesses of 40, 20, 10, and 5 μm were prepared for the calculations. Models without TSVs were used to examine the effect of the Si thickness. Then, using models including TSVs, the effect of the TSVs and the Si thickness dependency were investigated. The results indicated that ultra-thin Si stacking is suitable for multi-level stacking technology.

An innovative bumpless stacking with through silicon via for 3D Wafer-on-Wafer (WOW) integration

An adequate sequential etching though dielectrics, silicon and permanent adhesive material was successfully developed for the damascene interconnects in the face-to-back bumpless TSV Wafer on Wafer (WOW) processes. The induced bowing taken place at the etching of permanent adhesive was optimized and no void Cu metallization was achieved. According to those TSV technology, the upper and lower stacked wafers was electrically connected without bump electrodes. The improved process such as chemical mechanical planarization (CMP) of Cu re-distribution layer (RDL) is also developed successfully to provide uniform and straight line resistance distribution and reduce the loading of TSV over-etching to avoid the interconnect open issue.

Influence of wafer thinning process on backside damage in 3D integration

Ultra-thinning less than 10 microns of Si wafer is expected to realize small TSV feature which provides low aspect ratio and coupling capacitance. However, a detail of residual surface damage during thinning is unrevealed. In this paper, subsurface damage following wafer thinning from the back of 300 mm wafers using three different types of thinning process was investigated by means of Raman spectroscopy, XTEM, and Positron annihilation analysis, respectively. A coarse grinding generates significant rough subsurface ranged several micron and damage layer including amorphous and plastic-deformed Si along grinding topography. Fine grinding, second step of thinning, reduced those surface roughness and almost removed after thinning at least removal of 50 microns. However, plastic-deformed subsurface layer with a thickness of 100 to 200 nm are still remained which leaves an inside elastic stress layer ranging up to about 10 microns in depth. Chemical-Mechanical Polishing (CMP) process as a final step of thinning enables to remove residual damages such as structural defects and lattice strains after 1-5 microns thick polishing while vacancy-type defects only remain.