Ken Yamaguchi

A numerical model of avalanche breakdown in MOSFET's

An accurate numerical model of avalanche breakdown in MOSFETs is presented. Features of this model are a) use of an accurate electric-field distribution calculated by a two-dimensional numerical analysis, b) introduction of multiplication factors for a high-field path and the channel current path, and c) incorporation of the feedback effect of the excess substrate current induced by impact ionization into the two-dimensional calculation. This model is applied to normal breakdown observed in p-MOSFETs and to negative-resistance breakdown (snap-back or switchback breakdown) observed in short-channel n-MOSFETs. Excess substrate current generated from channel current by impact ionization causes a significant voltage drop across the substrate resistance in short-channel n-MOSFETs. This voltage forward-biases the source-substrate junction and increases channel current causing a positive feedback effect. This results in a decrease of the breakdown voltage and leads to negative-resistance characteristics. Current-voltage characteristics calculated by the present model agree very well with experimental results. Another model, highly simplified and convenient for device design, is also presented. It predicts some advantages of p-MOSFETs over n-MOSFETs from the standpoint of avalanche breakdown voltage, particularly in the submicrometer channel-length range.

Field-dependent mobility model for two-dimensional numerical analysis of MOSFET's

A field-dependent mobility model for use in two-dimensional numerical analysis of MOSFETs is proposed. This model takes into account two field components: One is the gate field which induces carriers in the inversion layer and the other is the drain field which transports carriers to the drain. Mobility is assumed to be a product of two functions, each of which includes only a field component perpendicular or parallel to the current flow (E_{\perp} or E_{\parallel}), that is \micro = \micro_{0} f (N_{B}, E_{\parallel})g(E_{\perp}), with\micro_{0}and NBbeing a constant and the impurity concentration, respectively. This equation is applied to calculate the mobility at each mesh point in the numerical analysis. The validity of the present model is demonstrated using several MOSFET structures, for example, conventional structures with short and long gate lengths, and offset-gate structrues with channel-doped layers. Reasonable agreement is found between calculated and experimental results under moderate bias conditions. Flat-band voltage, VFB, is assumed to be the only fitting parameter and is adjusted once for each set of samples. Quantitative agreement for short-channel MOSFETs is improved, typically by a factor of 2, and errors are within 20 percent with respect to the experiments.

Two-dimensional numerical analysis of stability criteria of GaAs FET's

Stability criteria of GaAs junction-gate FETs are studied by two-dimensional numerical analysis. The analysis covers the wide range of device geometry from the state of the art FET to the so-called Gunn effect digital devices. It is found that a GaAs FET exhibits either of the following three types of characteristics depending upon device geometry and doping concentration. First, for a thin channel with high doping concentration, the device tends to behave as a normal junction-gate FET with saturating current-voltage characteristics. This is even true when the n-l (device length) and n.d (device thickness) products exceed the previously accepted criteria for Gunn oscillation. Second, a stable negative resistance (SNR) is observed in devices with a moderate channel thickness. Third, for a thick channel, the device exhibits a Gunn oscillation with the domain propagating from the gate edge to the drain. These three categories of behavior are mapped on the nd plane with the help of simple analytic considerations. The map is found to compare well with experimental results.

A two-dimensional device simulator of semiconductor lasers

Abstract A two-dimensional simulator for aid in designing semiconductor lasers is developed. Poissons equation and the current continuity equations for electrons and holes as well as the wave equation and rate equation for photons are numerically solved. Heterojunctions and carrier degeneracy are rigorously treated, and analytical results on channeled-substrate-planar lasers are presented to demonstrate the simulator. Reasonable agreement is found between calculated and experimental results, and calculated results clarify precisely the operation mechanism of semiconductor lasers. The present work enables computer simulation for the first time to be a practical design aid in research and development of various kinds of semiconductor lasers.

Surface potential effect on gate—Drain avalanche breakdown in GaAs MESFET's

The surface potential effect on gate-drain avalanche breakdown in GaAs MESFETs is investigated with a two-dimensional device simulator. It is shown that the surface potential effect changes the potential distribution in GaAs MESFETs drastically and therefore plays an important role in determining drain breakdown voltage. In addition, two device structures producing high breakdown voltages, an offset gate structure and a recessed gate structure, are analyzed.

Drain conductance of junction gate FET's in the hot electron range

A new model is proposed for the drain conductance of J-FETs in the hot electron range. The model is based on a physical picture revealed through two-dimensional numerical analysis. The two-dimensional analysis shows that the electron concentration changes gradually at the boundary of a depleted region which is defined by a conventional theory. Because of this gradual change, electrons can remain after the pinch-off and contribute to the drain current. Although the high electric field causes the electron velocity to saturate, the drift velocity vector rotates into the x axis (source-to-drain) with the increase in the drain voltage. The increase in the x component Vxof the drift velocity gives rise to a small increase in drain current, that is, a finite drain conductance. The proposed model takes into account the above two essential features, gradual change in electron distribution, and the rotation of the velocity vector. This model is constructed in a single formulation which describes the current-voltage characteristics from the linear to the saturated drain-current region. Theoretical calculations agree quite well with the experiment on GaAs Schottky barrier gate FETs.

Modeling and characterization of polycrystalline-silicon thin-film transistors with a channel-length comparable to a grain size

A spatially discrete grain-boundary model for characterizing polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) is developed. This model was formulated for an interface state localized at the grain boundary. Threshold voltage (Vth) variation was analyzed using the model by changing the trap density and the location and number of grain boundaries in the poly-Si channel. The Vth shifts were found to be linearly dependent on the trap density (NGB) at the grain boundary and almost independent of the boundary location. The dependence of Vth on NGB was 0.15 V per trap density of 1012 cm−2 in long-gate TFTs. Since grain formation in the poly-Si channel is not controllable (it tends to be random), the threshold-voltage shift (ΔVth) predicted by the simulation will appear as statistical fluctuation in device fabrication. Simulation of the Vth fluctuation ranges showed that ΔVth increases with a decrease in channel length and will exceed 0.2 V in TFTs with a channel length of 1 μm or less when there is ...

Two-dimensional numerical simulation of Fermi-level pinning phenomena due to DX centers in AlGaAs/GaAs HEMTs

Fermi-level pinning phenomena due to DX centers in AlGaAs/GaAs HEMTs (high electron mobility transistors) are analyzed using two-dimensional numerical simulation based on a drift-diffusion model. A DX center model is introduced assuming Fermi-Dirac statistics for ionized donor density with the aluminum mole fraction dependence of the deep-donor energy level. The calculated results reveal that the decrease in transconductance of AlGaAs/GaAs HEMTs in a high-gate-bias region is caused by the existence of DX centers. This is because the Fermi level is pinned at deep-donor levels in the n-AlGaAs layer. Furthermore, the superiority of AlGaAs/InGaAs pseudomorphic HEMTs is discussed in terms of the Fermi-level pinning. >

Analysis of current leakage in InGaAsP/InP buried heterostructure lasers

The mechanism of current leakage at high temperatures in InGaAsP/InP buried heterostructure (BH) lasers with p-n-p-n current-blocking structures is analyzed using two-dimensional computer simulation. It is found that no junction in the blocking layers is reverse-biased and that current confinement is due to electrically floating regions in the blocking structures. To minimize the leakage current in these BH lasers, it is necessary to decrease the device width and the connection length between the blocking and cladding layers and to increase the doping level and thickness of the blocking layers. >

Cosmic-ray multi-error immunity for SRAM, based on analysis of the parasitic bipolar effect

This paper describes an investigation of cosmic-ray-induced multi-cell error (MCE) behavior in SRAMs through device- and circuit-level simulation methods developed on the basis that a parasitic bipolar effect is responsible for such errors. The first demonstration that the maximum number of cell errors per cosmic-ray strike depends on the number of cells between well contacts (Nc) is presented. The results are applied in an error checking and correction (ECC) design guideline for the handling of cosmic-ray-induced multi-cell errors. A new architecture is proposed, in which matching of addresses to memory cells is consideration of the Nc. This architecture reduced soft error rate (SER) for an SRAM fabricated by using 0.13-/spl mu/m CMOS technology by 88%.