Kenichi Shimomura

Approaches to extra low voltage DRAM operation by SOI-DRAM

The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-/spl mu/m 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V.

4-μm pixel CMOS image sensor with low-image lag and high-temperature operability

We present a development of a high image quality color VGA CMOS image sensor with 4-micron pixel pitch, especially focusing on reduction of image lag. In order to eliminate image lag, improvement of charge transfer efficiency from photodiode (PD) to floating diffusion (FD) is a key point. We implemented two novel techniques for this purpose. The first technical point is an optimum design of pixel layout, which provides both high fill factor and a large channel width of transfer gate transistor (TG). We achieved both high fill factor of 42% without microlens and large TG channel width of 1.79um, which is 2.4 times larger than the minimum channel width allowed by design rule. The second technical point is a new device structure of TG by a novel Boron implantation process. This brings a wide path of charge transfer from PD to FD. High-quality images with low image lag, less than 0.75%, were obtained. Moreover, we also achieved a CMOS image sensor with high-temperature operability. In order to stabilize an adequate black level, we developed a new scheme of a black level control that adjusts offset voltages of amplifiers with feedback signal from analog-digital converter (ADC). An adequate black level was realized up to 100 degrees centigrade for a 5.6-micron pitch monochrome CIF sensor.