Makoto Hanawa

A 4.3 ns 0.3 /spl mu/m CMOS 54/spl times/54 b multiplier using precharged pass-transistor logic

A 54/spl times/54 b multiplier with 4.3 ns latency at 2.5 V supply and a 16.96 mm/sup 2/ active area is implemented in 0.3 /spl mu/m CMOS with 6.5 nm gate oxide and four-layer metal. This 4.3 ns latency multiplier is for a floating-point unit (FPU) on a CMOS RISC processor capable of performing IEEE double precision multiply operations in three pipelined stages at 400 MHz (7.5 ns latency and 2.5 ns throughput). This multiplier consists of a 54/spl times/54 b carry-save adder tree and a 108 b carry propagation adder. This multiplier achieves 4.3 ns performance using a modified Wallace tree implemented from 4:2 compressors with precharged pass-transistor circuits, radix-2 Booth encoding with an unbalanced buffer for generating select signals, and a short-path carry-lookahead adder.

A superscalar RISC processor with 160 FPRs for large scale scientific processing

We have developed a superscalar RISC processor for the super technical server HITACHI SR8000. The processor includes architectural features specialized in scientific applications, in which massive amounts of data in the main memory must be processed. These features are a slide-windowed-registers scheme and a simultaneous execution of up to 16 prefetch instructions. The slide-windowed-registers scheme enables instructions of the processor to access any of 160 floating point registers (FPRs). The execution mechanism for prefetch instructions produces high efficiency of the out-of-order superscalar processor despite the long latency of the main memory. A logic simulation showed that the performance of the processor reaches over 3 floating-point operations per cycle and the memory throughput of over 12 bytes per cycle.

A 1000 MIPS BiCMOS microprocessor with superscalar architecture

A 1000 MIPS computer, integrated on a single chip and experimentally developed using 0.3- mu m self-aligned BiCMOS technology, is described. It features superscalar processing and pipelined access of interleaved secondary cache. The authors describe circuit techniques of the cache, TLB, register, file, and ALU (arithmetic and logic unit) operating at 250 MHz.<<ETX>>

On-chip multiple superscalar processors with secondary cache memories

The development of an experimental high-performance microprocessor chip based on a 0.3- mu m BiCMOS technology is discussed. It is designed to operate at a 250-MHz clock rate. It includes two processors, each of which executes two instructions in parallel. The chip performs 1000 MIPS when instructions and data are fetched from primary caches. It also includes a four-wave interleaved secondary cache assessed in parallel according to a split-bus protocol, to reduce shared memory conflicts. The VLSI architecture and design results of this chip are described.<<ETX>>

Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor

A stack cache scheme in combination with a general register set is presented as an alternative to the register file. Two cache memories, a 1-K byte code cash and a four-entry cache for branch instructions, are also embedded to accelerate the pipeline stream. This scheme has been implemented and evaluated on a 32-bit microprocessor, the Hitachi H32/200, based on TRON (The Real-time Operating system Nucleus) specifications. This processor contains 730 K transistors in 1.0- mu m CMOS. It performs 6 to 7 MIPS (million instruction per second) at a 20-MHz clock rate.<<ETX>>

A concurrent fault detection method for superscalar processors

The authors describe a method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method makes use of the No Operation (NOP) instructions slots that sometimes fill some of the pipelines (stages) in an ILP processor. The authors show the practical application of this method to a superscalar RISC processor. For this processor, branch addresses, execution of certain instructions (store/load) and resource conflicts that force the inclusion of NOPs are the cases exploited to test its pipelines. The NOPs are replaced by an effective instruction running in another pipeline. This allows the checking of the processors pipelines by the comparison of the outputs of their stages during the execution of the replicated instruction.<<ETX>>

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules

Low-voltage high-machine-cycle BiCMOS circuit techniques for deep submicron BiCMOS RISC (reduced instruction set computer) processors are discussed. The feedback massive-input logic (FML) concept reduces by 3-4 times the number of transistors and the power within the framework of fully static logic. A quasi-complementary buffer circuit provides unprecedentedly excellent low-supply-voltage performance even below 3 V. Sequential circuits are enabled to operate at low voltages with good performance leverage over CMOS by the novel QC-BiCMOS flip-flop. It is demonstrated that the BiCMOS continues to have superior performance over CMOS in the sub-0.3- mu m sub-3-V region, which promises 250-MHz-level parallel processing RISCs and ASICs (application-specific integrated circuits).<<ETX>>