Kerry Maize

Steep-slope hysteresis-free negative capacitance MoS 2 transistors

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal–oxide–semiconductor field-effect transistor (MOSFET) at 60 mV dec−1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption1,2. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier3. Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel4–12. Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm−1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.A field-effect MoS2 transistor with a negative capacitor in its gate shows stable, hysteresis-free performance characterized by a sub-thermionic sub-threshold slope.

Direct Observation of Self-Heating in III–V Gate-All-Around Nanowire MOSFETs

Gate-all-around (GAA) MOSFETs use multiple nanowires (NWs) to achieve target

β-Ga2O3 on insulator field-effect transistors with drain currents exceeding 1.5 A/mm and their self-heating effect

I_{\mathrm{{\scriptscriptstyle ON}}}

Super-Joule heating in graphene and silver nanowire network

, along with excellent 3-D electrostatic control of the channel. Although the self-heating effect has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and specialized test structures, do not offer adequate spatiotemporal resolution. In this paper, we develop an ultrafast high-resolution thermoreflectance (TR) imaging technique to: 1) directly observe the increase in local surface temperature of the GAA-FET with different number of NWs; 2) characterize/interpret the time constants of heating and cooling through high-resolution transient measurements; 3) identify critical paths for heat dissipation; and 4) detect in situ time-dependent breakdown of individual NW. Combined with the complementary approaches that probe the internal temperature of the NWs, the TR-images offer a high-resolution map of self-heating in the surround-gate devices with unprecedented precision, necessary for the validation of electrothermal models and the optimization of devices and circuits. In addition, we develop the simple compact model of the complex structure, which can explain experimental observations and can provide the internal temperature of the NWs.

Direct observation of self-heating in III–V gate-all-around nanowire MOSFETs

We have demonstrated that depletion/enhancement-mode β-Ga2O3 on insulator field-effect transistors can achieve a record high drain current density of 1.5/1.0 A/mm by utilizing a highly doped β-Ga2O3 nano-membrane as the channel. β-Ga2O3 on insulator field-effect transistor (GOOI FET) shows a high on/off ratio of 1010 and low subthreshold slope of 150 mV/dec even with 300 nm thick SiO2. The enhancement-mode GOOI FET is achieved through surface depletion. An ultra-fast, high resolution thermo-reflectance imaging technique is applied to study the self-heating effect by directly measuring the local surface temperature. High drain current, low Rc, and wide bandgap make the β-Ga2O3 on insulator field-effect transistor a promising candidate for future power electronics applications.

High Resolution Thermal Characterization and Simulation of Power AlGaN/GaN HEMTs Using Micro-Raman Thermography and 800 Picosecond Transient Thermoreflectance Imaging

Transistors, sensors, and transparent conductors based on randomly assembled nanowire networks rely on multi-component percolation for unique and distinctive applications in flexible electronics, biochemical sensing, and solar cells. While conduction models for 1-D and 1-D/2-D networks have been developed, typically assuming linear electronic transport and self-heating, the model has not been validated by direct high-resolution characterization of coupled electronic pathways and thermal response. In this letter, we show the occurrence of nonlinear “super-Joule” self-heating at the transport bottlenecks in networks of silver nanowires and silver nanowire/single layer graphene hybrid using high resolution thermoreflectance (TR) imaging. TR images at the microscopic self-heating hotspots within nanowire network and nanowire/graphene hybrid network devices with submicron spatial resolution are used to infer electrical current pathways. The results encourage a fundamental reevaluation of transport models for network-based percolating conductors.

Thermodynamic Studies of β-Ga2O3 Nanomembrane Field-Effect Transistors on a Sapphire Substrate

Gate-all-around MOSFETs use multiple nanowires to achieve target ION, along with excellent 3D electrostatic control of the channel. Although self-heating effect (SHE) has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and specialized test structures, do not offer adequate spatio-temporal resolution. In this paper, we develop an ultra-fast, high resolution thermo-reflectance (TR) imaging technique to (i) directly observe the increase in local surface temperature of the GAA-FET with different number of nanowires (NWs), (ii) characterize/interpret the time constants of heating and cooling through high resolution transient measurements, (iii) identify critical paths for heat dissipation, and (iv) detect in-situ time-dependent breakdown of individual NW. Our approach also allows indirect imaging of quasi-ballistic transport and corresponding drain/source asymmetry of self-heating. Combined with the complementary approaches that probe the internal temperature of the NW, the TR-images offer a high resolution map of self-heating in the surround-gate devices with unprecedented precision, necessary for validation of electro-thermal models and optimization of devices and circuits.

Fundamental trade-off between short-channel control and hot carrier degradation in an extremely-thin silicon-on-insulator (ETSOI) technology

Self-heating in gallium nitride based high frequency, high electron mobility power transistors (GaN HEMTs) is inspected using micro-Raman thermography and 800 picosecond transient thermoreflectance imaging. The two methods provide complementary temperature information inside the semiconductor and on top metal layers of the GaN HEMT. Self heating is measured under both steady-state and ultra-fast pulsed transient operation with submicron spatial resolution, 50 milliKelvin temperature resolution, and nanosecond time resolution. Fine grain electrothermal modeling of the HEMT steady state and transient self-heating are presented alongside measurements. Large spatial and temporal temperature gradients are quantified. Deviations due to unknown parameters are discussed.

Evidence of Universal Temperature Scaling in Self-Heated Percolating Networks

The self-heating effect is a severe issue for high-power semiconductor devices, which degrades the electron mobility and saturation velocity, and also affects the device reliability. On applying an ultrafast and high-resolution thermoreflectance imaging technique, the direct self-heating effect and surface temperature increase phenomenon are observed on novel top-gate β-Ga2O3 on insulator field-effect transistors. Here, we demonstrate that by utilizing a higher thermal conductivity sapphire substrate rather than a SiO2/Si substrate, the temperature rise above room temperature of β-Ga2O3 on the insulator field-effect transistor can be reduced by a factor of 3 and thereby the self-heating effect is significantly reduced. Both thermoreflectance characterization and simulation verify that the thermal resistance on the sapphire substrate is less than 1/3 of that on the SiO2/Si substrate. Therefore, maximum drain current density of 535 mA/mm is achieved on the sapphire substrate, which is 70% higher than that on the SiO2/Si substrate due to reduced self-heating. Integration of β-Ga2O3 channel on a higher thermal conductivity substrate opens a new route to address the low thermal conductivity issue of β-Ga2O3 for power electronics applications.

Thermoreflectance imaging of electromigration evolution in asymmetric aluminum constrictions

Extremely thin silicon-on-insulator (ETSOI) structure has been developed to improve gate control and to suppress the short-channel effect (SCE) associated with bulk MOSFET. However, since self-heating in ETSOI may compromise both performance and reliability, a careful analysis of the trade-off between short-channel control and self-heating is needed. In this paper, we (i) characterize channel and surface self-heating of a ETSOI technology as a function of channel thickness (Tsi) and length (Lch) using electrical and optical methods, respectively; (ii) theoretically interpret the trade-off between gate controllability and self-heating effects, (iii) correlate HCI degradation to the degree of self-heating, and (vi) find distinctive universality of HCI degradation (as a function of Tsi and Lch) that enables a long term reliability projection. We conclude that the trade-off between HCI and channel control suggests that thinnest channel may not be optimum; and that the universality of HCI degradation would hold only if self-heating is accounted for.