Muhammad A. Wahab

Using nanoscale thermocapillary flows to create arrays of purely semiconducting single-walled carbon nanotubes

Among the remarkable variety of semiconducting nanomaterials that have been discovered over the past two decades, single-walled carbon nanotubes remain uniquely well suited for applications in high-performance electronics, sensors and other technologies. The most advanced opportunities demand the ability to form perfectly aligned, horizontal arrays of purely semiconducting, chemically pristine carbon nanotubes. Here, we present strategies that offer this capability. Nanoscale thermocapillary flows in thin-film organic coatings followed by reactive ion etching serve as highly efficient means for selectively removing metallic carbon nanotubes from electronically heterogeneous aligned arrays grown on quartz substrates. The low temperatures and unusual physics associated with this process enable robust, scalable operation, with clear potential for practical use. We carry out detailed experimental and theoretical studies to reveal all of the essential attributes of the underlying thermophysical phenomena. We demonstrate use of the purified arrays in transistors that achieve mobilities exceeding 1,000 cm(2) V(-1) s(-1) and on/off switching ratios of ∼10,000 with current outputs in the milliamp range. Simple logic gates built using such devices represent the first steps toward integration into more complex circuits.

Microwave purification of large-area horizontally aligned arrays of single-walled carbon nanotubes

Recent progress in the field of single-walled carbon nanotubes (SWNTs) significantly enhances the potential for practical use of this remarkable class of material in advanced electronic and sensor devices. One of the most daunting challenges is in creating large-area, perfectly aligned arrays of purely semiconducting SWNTs (s-SWNTs). Here we introduce a simple, scalable, large-area scheme that achieves this goal through microwave irradiation of aligned SWNTs grown on quartz substrates. Microstrip dipole antennas of low work-function metals concentrate the microwaves and selectively couple them into only the metallic SWNTs (m-SWNTs). The result allows for complete removal of all m-SWNTs, as revealed through systematic experimental and computational studies of the process. As one demonstration of the effectiveness, implementing this method on large arrays consisting of ~20,000 SWNTs completely removes all of the m-SWNTs (~7,000) to yield a purity of s-SWNTs that corresponds, quantitatively, to at least to 99.9925% and likely significantly higher.

Impact of nanowire variability on performance and reliability of gate-all-around III-V MOSFETs

Gate-all-around (GAA) transistors use multiple parallel nanowires to achieve the desired ON current. The fabrication and performance of GAA transistors have been reported, however, a fundamental consideration, namely, the scaling and variability of transistor performance as a function of the number of parallel NWs is yet to be discussed. In this paper, we (i) examine how the overall performance matrix (e.g., ION, IOFF, Vth, SS, RC) depends on the number of parallel NWs, (ii) theoretically interpret the results in terms of variability and self-heating among the NWs, (iii) compare the reliability of multiple NW devices (ΔVth, ΔSS, both stress and recovery) with a planar device of similar technology. We find that the self-heating and NW-to-NW variability are reflected in novel properties of variability and reliability of GAA transistors that are neither anticipated nor observed in the corresponding planar technology.

Direct Observation of Self-Heating in III–V Gate-All-Around Nanowire MOSFETs

Gate-all-around (GAA) MOSFETs use multiple nanowires (NWs) to achieve target

Electrostatic dimension of aligned-array carbon nanotube field-effect transistors.

I_{\mathrm{{\scriptscriptstyle ON}}}

3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature

, along with excellent 3-D electrostatic control of the channel. Although the self-heating effect has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and specialized test structures, do not offer adequate spatiotemporal resolution. In this paper, we develop an ultrafast high-resolution thermoreflectance (TR) imaging technique to: 1) directly observe the increase in local surface temperature of the GAA-FET with different number of NWs; 2) characterize/interpret the time constants of heating and cooling through high-resolution transient measurements; 3) identify critical paths for heat dissipation; and 4) detect in situ time-dependent breakdown of individual NW. Combined with the complementary approaches that probe the internal temperature of the NWs, the TR-images offer a high-resolution map of self-heating in the surround-gate devices with unprecedented precision, necessary for the validation of electrothermal models and the optimization of devices and circuits. In addition, we develop the simple compact model of the complex structure, which can explain experimental observations and can provide the internal temperature of the NWs.

Origin and implications of hot carrier degradation of Gate-all-around nanowire III–V MOSFETs

Accurate electrostatics modeling of nanotubes (NTs)/nanowires (NWs) has significant implications for the ultimate scalability of aligned-array NT/NW field-effect transistors (FETs). The analysis to date has focused on limits of capacitive coupling between the 1D channel and 2D gate that is strictly relevant only in the linear response operation of NT/NW-FETs. Moreover, the techniques of electrostatic doping by independent gates that cover only part of the channel are widely used, but the nature of its electrostatic coupling has not been explored. In this paper, we use a three-dimensional, self-consistent model for NT/NW-FETs to interpret the essence of electrostatic coupling with complex configuration of electrode geometries. The interplay between 3D electric fields and its 1D termination onto the NTs/NWs suggests surprising complexity of electrostatic interaction not captured in simpler models. This coupling can change the performance metrics such as ON and OFF currents by orders of magnitude depending on (1) NT/NW density, (2) bias voltage, and (3) gate overlap length. Remarkably, this parasitic coupling persists regardless of the gate oxide thickness, changes in dielectric constant, and/or the width of the diameter distribution of NTs/NWs. The predictions of the model are systematically validated by a series of experiments.

Direct observation of self-heating in III–V gate-all-around nanowire MOSFETs

Excellent electrostatic control offered by gate-all-around (GAA) geometry makes multinanowire (multi-NW) MOSFET a promising candidate for sub-10-nm technology nodes. Unfortunately, the GAA geometry is susceptible to the increased self-heating due to poor heat dissipation from the nanowires (NWs) to the substrate. Therefore, an understanding of spatio-temporal temperature rise, AT(x, y, z; t), at the NW level is important for predicting activity-induced variability within an IC, as well as characterization of various reliability issues, such as, NBTI, PBTI, HCI, and TDDB that depend sensitively on self-heating. In this paper, a 3-D electrothermal simulation model is developed to explore and interpret self-heating and heat dissipation in GAA devices. Our results identify complex heat dissipation pathways characterized by multiple time constants. First, the nanowires heat up quickly (τGAA-NW ~ nSec), then heat spreads all over the gate contact pad (τG-pad ~ 100 nSec), and finally, the heat exits through the heat sink at the bottom of the substrate (τsub ~ mSec). A systematic thermoreflectance measurement of temperature helps us to identify the time constants, and validates the model. Our results have implications for the design, characterization, circuit-operation, and reliability of high-performance GAA devices.

Direct current injection and thermocapillary flow for purification of aligned arrays of single-walled carbon nanotubes

Although ultra-scaled III-V Gate-all-around (GAA) nanowire (NW) MOSFETs have been studied for their immunity to short channel effects, the degradation mechanisms, such as, hot carrier injection (HCI) in the NW MOSFETs are yet to be studied systematically. In this paper, we examine how HCI affects the NW device performance (ΔVth, ΔSS in both stress and recovery) at different bias conditions, and demonstrate that, unlike positive bias temperature instability (PBTI) in NMOS transistors, the HCI degradation is dominated by charge trapping. We analyze the implications of spatial charge trapping on device performance through experiments and simulation. We find that the distinctive features of HCI degradation of GAA NWs structure can be consistently interpreted by a Sentaurus™-based TCAD simulation.

Implications of Electrical Crosstalk for High Density Aligned Array of Single-Wall Carbon Nanotubes

Gate-all-around MOSFETs use multiple nanowires to achieve target ION, along with excellent 3D electrostatic control of the channel. Although self-heating effect (SHE) has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and specialized test structures, do not offer adequate spatio-temporal resolution. In this paper, we develop an ultra-fast, high resolution thermo-reflectance (TR) imaging technique to (i) directly observe the increase in local surface temperature of the GAA-FET with different number of nanowires (NWs), (ii) characterize/interpret the time constants of heating and cooling through high resolution transient measurements, (iii) identify critical paths for heat dissipation, and (iv) detect in-situ time-dependent breakdown of individual NW. Our approach also allows indirect imaging of quasi-ballistic transport and corresponding drain/source asymmetry of self-heating. Combined with the complementary approaches that probe the internal temperature of the NW, the TR-images offer a high resolution map of self-heating in the surround-gate devices with unprecedented precision, necessary for validation of electro-thermal models and optimization of devices and circuits.