Olli Viitala

A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS

This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.

A 5-bit 1-GS/s Flash-ADC in 0.13-μm CMOS Using Active Interpolation

This work presents a 5-bit 1-GS/s flash-ADC in 0.13-μm CMOS technology. An active interpolation topology is used in the comparator inputs to reduce power consumption and input capacitance of the converter. Operating at 1.056-GS/s the ADC consumes 46 mW of power from a 1.2 V supply and provides an ENOB of 4.73 bits and an SFDR of 43.2 dBc at a signal frequency of 102 MHz. The ADC has an ERBW of 470 MHz and a FoM of 1.8 pJ/convstep. Area consumption for the converter is 0.2 mm2.

A 60-GHz CMOS receiver with an on-chip ADC

A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is −38.5 dBm.

Analysis and Design of N-Path Filter Offset Tuning in a 0.7–2.7-GHz Receiver Front-End

N-path techniques have become a popular candidate alternative to external pre-selection filtering in wireless receivers. Their main attraction lies in enabling tunable on-chip high- Q filters, with straightforward migration from one CMOS node to another. However, parasitic capacitance at the N-path filter input offsets the bandpass response from the desired center frequency in wideband circuits. In this paper, we focus on an LNA-first receiver and show that the offset at the LNA output varies in magnitude depending on LNA and filter load impedance properties. An offset-tuning approach is then evaluated for its effects on receiver gain and noise and to obtain design guidelines. We propose a digitally controllable implementation that preserves front-end gain and linearity, with a small penalty on receiver NF. A programmable 0.7-2.7-GHz front-end in 40-nm CMOS verifies the functionality. At 1.7 GHz, the front-end has a gain of 37 dB, a NF of 5.2 dB, and an out-of-band IIP3 of +1 dBm.

Characteristics of LNA Operation in Direct Delta–Sigma Receivers

This brief analyzes the dual role and operation of the low noise amplifier (LNA) in the recently introduced direct delta-sigma receiver (DDSR). First, the LNA functions as a transconductor in an integrator stage, and in this role, we explore the effects of LNA output impedance on quantization noise shaping by the system. In the second role of a voltage preamplifier, we show how the closed-loop DDSR structure impacts LNA voltage gain and system noise. LNA and system properties are thus intertwined and lead to the need for careful codesign. The reliability of the utilized continuous-time DDSR approximation is verified by simulating a sample receiver model.

A 2.5-GHz Receiver Front-End With Q-Boosted Post-LNA N-Path Filtering in 40-nm CMOS

This paper presents the analysis, design, and measurements of a 2.5-GHz receiver front-end in a 40-nm CMOS technology. The front-end utilizes RLC-resonator quality factor (Q) boosting and four-phase N-path filtering to improve the blocker filtering capabilities of the low-noise amplifier (LNA). Systematic analysis is performed in order to obtain a thorough design approach. Particular attention is paid to the passive mixer switches in the RLC case, for which we show that minimum switch resistance does not provide best noise figure (NF), nor best relative blocker attenuation. Moreover, the N-path filter extends the stable operating region of a Q-boosted LNA, and adding a noisy Q-boosting circuit can actually improve the receiver NF in practical realizations. The experimental CMOS front-end is flip-chip packaged, and a parasitic-aware input matching method for the electrostatic-discharge-protected LNA is proposed, analyzed, and verified. In nominal operation, the programmable front-end achieves a measured gain of 39 dB, an NF of 3.5 dB, and an out-of-band input-referred third order intercept point of > 0 dBm, while consuming 48 mA from a 1.1-V supply.

N-path g m C filter modeling and analysis for direct delta-sigma receiver

This paper presents the analysis and a model for obtaining the delta-sigma loop filter coefficients of a direct delta-sigma receiver (DDSR). The analysis is done by modeling a key element of the DDSR, the N-path filter, with an s-plane transfer function in the baseband. The s-plane model includes the most important non-idealities, such as switch resistances and the limited output resistances of the RF-stages. The model allows the designer to approximate the key parameters for DDSR and enables the optimization of the DDSR performance. As an example, the coefficients of a third-order DDSR are obtained by examining the s-plane and the corresponding z-plane signal and quantization noise transfer functions. The results are evaluated with circuit level simulations.

A wideband under-sampling blocker detector with a 0.7–2.7 GHz mixer-first receiver

This paper presents a low power wideband blocker detector consisting of an under-sampling SAR ADC connected to the RF input node of a wideband mixer-first receiver. The original carrier frequency of the blocker is determined from folded spectra by using three FFTs sampled at different rates whose ratios correspond to prime numbers. The detector is targeted for blocker power levels between 0 and -30 dBm within frequency range of 0.7-2.7 GHz. The achieved ADC maximum SNDR of 28 dB, together with 10 dB input buffer gain control, provide sufficient blocker detection sensitivity in the desired range. The measured sampled input signal spectra show the designed circuits capability to simultaneously detect narrowband and wideband blockers. The reconstructed folded spectrum shows the original blocker frequencies. The power consumption of the wideband detector is only 7 mW, while the receiver consumes 42 mW.

Next-Generation RF Front-End Design Methods for Direct

RF-to-digital conversion is a recent approach to digital-intensive wireless receiver operation. Such converters often employ delta-sigma (ΔΣ) modulation to transcend the traditional divide between receiver RF front-ends and baseband analog-to-digital converters (ADC). Research on the direct delta-sigma receiver (DDSR) architecture is one example of the emergence of next-generation ΔΣ modulators. It embeds a direct conversion receiver front-end as part of a feedback-type ΔΣ modulator structure with an active loop filter, which extends ADC operation to RF and changes the role of the low-noise amplifier (LNA) and mixing stages. RF-to-digital converters thus merge the two formerly separate design domains, requiring a paradigm shift in both RF and ADC design methods. Accordingly, this paper uses the DDSR as an example to bridge the gap between RF and ADC design, by providing a systematic understanding of the role, modeling, and design strategy of the related complete RF front-end. Most importantly, the analysis produces new design equations that link analog RF stage properties to their continuous-time (CT) ΔΣ modulator coefficients, thus providing a useful circuit design tool.

\Delta\Sigma

This paper presents the modeling of a close-proximity communication link with a lumped circuit representation. The inter-chip data transfer is performed via capacitive couplings between the top facing dies (flip-chip arrangement). The problems occuring in such a wireless communications are introduced. Based on three-dimensional (3D) electromagnetics (EM) simulations, a lumped circuit model for the capacitive link has been developed. The effect of cross-talk between adjacent channels is also considered in the model and discussed.