Hai P. Longworth

An advanced multichip module (MCM) for high-performance UNIX servers

In 2001, IBM delivered to the marketplace a high-performance UNIX?®-class eServer based on a four-chip multichip module (MCM) code named Regatta. This MCM supports four POWER4 chips, each with 170 million transistors, which utilize the IBM advanced copper back-end interconnect technology. Each chip is attached to the MCM through 7018 flip-chip solder connections. The MCM, fabricated using the IBM high-performance glass-ceramic technology, features 1.7 million internal copper vias and high-density top-surface contact pad arrays with 100-?µm pads on 200-?µm centers. Interconnections between chips on the MCM and interconnections to the board for power distribution and MCM-to-MCM communication are provided by 190 meters of co-sintered copper wiring. Additionally, the 5100 off-module connections on the bottom side of the MCM are fabricated at a 1-mm pitch and connected to the board through the use of a novel land grid array technology, thus enabling a compact 85-mm ?? 85-mm module footprint that enables 8- to 32-way systems with processors operating at 1.1 GHz or 1.3 GHz. The MCM also incorporates advanced thermal solutions that enable 156 W of cooling per chip. This paper presents a detailed overview of the fabrication, assembly, testing, and reliability qualification of this advanced MCM technology.

C4NP technology: Manufacturability, yields and reliability

As a part of IBM movement from Pb-rich solders to Pb-free solder, a new low cost process has been developed to deposit the solder to a capture, or under bump metal (UBM) pad, with Suss MicroTech Inc as the equipment partner. The controlled collapsed chip connection new process (C4NP) has moved, over the last 2 years, from development into manufacturing for 300 mm wafers. During this transition, a great number of process improvements have resulted in high fabrication yields. Manufacturing robustness has been achieved by clearly identifying the processes which affect the C4 structural integrity. The solder composition has been optimized to improve its mechanical properties as well as low alpha emission rate requirement. Sector partitioning methodology was used to obtain root cause for various defects which then, through replication studies, were confirmed. Key process improvements in the capture pad build, mold fabrication, and mold fill tool have been accomplished as the process has matured. Thermal undercut was identified as a mechanism of Cu seed consumption when no top Cu was available on top of the Ni UBM. C4NP technology can produce yields comparable to that of electroplated C4 Bumps. Yield learning model shows a 15% defect reduction per month since the start of the C4NP program. Technology qualification for 300 mm wafers with 200um and 150 um pitch Pb-free C4 bumps has been successfully completed.

Thin-film multichip module packages for high-end IBM servers

A new generation of multilevel thin-film packages has been developed for IBM high-end S/390® and AS/400® systems. Thin-film structures in these packages are nonplanar and can be fabricated by either pattern electroplating or subtractive etching. Selection criteria for choice of fabrication methods are discussed in terms of electrical performance requirements, ground rules, manufacturability, and cost issues. Two problems encountered in the development phase of the nonplanar thin-film structures were 1) accelerated etching of plated Cu features during Cu seed etching, and 2) corrosion of the bottom-surface metallurgy during etching of Cr at the top surface. Effective solutions were developed on the basis of underlying electrochemical phenomena. Finally, reliability stress procedures used to qualify these packages and results of these procedures are presented.

C4NP as a High-Volume Manufacturing Method for Fine-Pitch and Lead-Free FlipChip Solder Bumping

More and more high-end microelectronic devices are being packaged by using solder bumps as the method of interconnection. The two main technologies are flipchip in package (FCiP) and wafer level chip scale package (WLCSP). The main difference is that FCiP devices are placed on a substrate which then interconnects to the PC board (PCB). WLCSP devices connect directly onto the board. There are various solder bumping technologies used in volume production. These include electroplating, solder paste printing, evaporation and the direct attach of preformed solder spheres. FCiP demands many small bumps on tight pitch whereas WLCSP typically requires much larger solder bumps. All these established technologies have important limitations for fine pitch bumping especially when it comes to lead-free solder alloys. The most commonly used method of generating fine-pitch solder bumps is by electroplating the solder. This process is difficult to control and costly, especially when it comes to lead-free solder alloys. These challenges in the transition to lead-free solder bumping has led the European Union to grant exemptions from the ban of lead in certain solder bumping applications. However, the pressure to move to lead-free continues for the entire industry. C4NP (C4-new process) is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). Mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost solution for both, fine-pitch FC in package as well as WLCSP bumping applications. This paper provides a summary of manufacturing and reliability results of C4NP bumped high-end logic devices and how they compare to electroplated lead-free solder bumps. It discusses the relevant process equipment technology and the novel requirements to run a HVM (high volume manufacturing) C4NP process. The paper also talks about the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is provided by IBMs packaging operation at the Hudson Valley Research Park in East Fishkill, NY

Development and Implementation of C4NP Technology for 300 mm Wafers

Considerable work is ongoing worldwide on developing lead-free solutions for electronics industry to meet the needs of RoHs requirements. This paper describes the development and implementation of lead-free C4 interconnects for 300 mm wafers using, C4NP technology at IBM with equipment partnership with Suss MicroTech Inc. Key process modules of C4NP technology are: (a) UBM pads fabrication using simple unit processes in back end of the line semiconductor manufacturing facility, (b) Solder melt filling of glass molds with cavities in solder fill tool and inspection, (c) C4 bump transfer to UBM pads on wafers using vaporized flux process in solder transfer tool, (d) Final inspections and electrical tests. This process technology for C4 bumping eliminates the need for solder or solder alloy plating and provides wider latitude for selecting solder composition. For example, solders can be selected for improved mechanical properties and, or low alpha emission requirements. This can be accomplished by simple changing of mold fill head. Primary efforts of this study are focused on four key elements: (1) Development of unit processes for UBM pad patterning and solder transfer processing, (2) chip/organic laminate module builds, using industry standard bond and assembly processes, (3) selection of specific test vehicle wafers with 200 um pitch pads and over 1.25 million C4 bumps, and (4) extensive reliability testing of modules with JDEC and IBM internal standards. Modules with test vehicle chips as well as product chips have shown excellent reliability data, comparable to that of high lead electroplated C4 bumps, and meet application requirements. In order to assess manufacturing robustness and yields, sector partitioning studies were undertaken to understand the effects of unit process windows and defect densities. Results show that C4NP technology can produce yields comparable to that of electroplated C4 Bumps. Technology qualification studies have been successfully completed. Thus, enabling the path for manufacturing ramp up. This technology is extendable to higher density C4 interconnects and product qualifications studies on C4 bumps on 150 um pitch are ongoing. IBM is adapting this technology for 300 mm lead-free applications.

Reliability evaluation of multilevel thin film structures

IBM Microelectronics has evaluated the reliability of structures built by various processes which we developed for multilevel thin film (MLTF) applications. Two distinct processes were used for the building of conformal copper-polyimide structures on alumina ceramic: Laser ablation of the polyimide for via patterning and wiring defined by subtractive etching of Cr/Cu/Cr, and photosensitive polyimide for via patterning and wiring defined by electroplating through a resist. Reliability evaluation was performed on test-vehicles with both MLTF processes by a combination of IBM standard and MIL-STD-883 stress procedures. These stresses were designed to monitor any potential reliability problems due to metal migration, corrosion (or contamination), metal fatigue, and poor step coverage. Electrical measurements were done before, during, and after stress to check for opens and inter and intralevel shorts. At completion of stressing, no failures were observed in either type of test vehicles. This indicates that both processes meet or exceed IBM current product reliability standards.<<ETX>>

Engineered thermal interface material

The power dissipation and device junction temperature control in high end processors, stacked and hybrid packages, test and burn-in systems, LED devices, etc. present challenges in cooling. Many types of consumer devices and sensors are proliferating. All these applications require an ongoing improvement in thermal management. A key aspect of electronic package cooling is the thermal interface material used between the heat generating component and the heat spreader or heat sink. High performance thermal interface materials enable Tj reduction, device performance improvement and/or lower power operation. Organic laminate packages are especially vulnerable to package failures driven by CTE mis-match driven stresses and strains. Choice of TIM is therefore critical in addressing not only the thermal challenges, but also the mechanical weaknesses of a laminate package. Often a polymeric TIM with adequate compliance to address the mechanical issues and yet having a high thermal performance is desired. The properties of the TIM, such as the modulus, elongation, adhesion to both surfaces and thermal impedance, have to be carefully selected for optimum performance in a package. In this paper, we report the development of an industry leading, high performance thermal interface material. The project involved engineering the matrix polymer properties to systematically vary the composite modulus and die shear strength and meet the desired TIM property objectives. Methodical material property characterizations were carried out for feedback and formulation improvement. A few formulations were developed with TIM1 impedance in the range of 0.04-0.07 cm2C/W. The thermal performance was measured on thermal test vehicles. Material and process parameters were investigated to minimize voiding. Material characterization and thermal performance results are presented in this paper.

C4NP - Lead Free Flip Chip Solder Bumping Manufacturing and Reliability Data

To meet future requirements for cost, size, weight and electrical performance, microelectronic packaging is moving from wire bonds to solder bumps as the preferred method of interconnection from the device to the chip carrier or card. Flip chip in package (FCiP) requires many small bumps on tight pitch whereas wafer level chip scale packaging (WLCSP) typically requires much larger solder bumps on a greater pitch. Electroplating, solder paste printing and the direct attach of preformed solder spheres are technologies commonly used in volume production for wafer bumping. Each of these techniques has limitations in scaling from fine pitch FCiP to WLCSP. Electroplating is better suited to fine pitch, whereas solder paste printing and solder sphere attachment work well for coarser pitches. C4NP (controlled collapse chip connection new process) has proven to be suitable for this entire range of solder bump pitch. C4NP is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications. This paper summarizes the latest manufacturing and reliability data for high-end logic device packaging using 300mm wafers bumped with C4NP. This includes initial reliability data for C4NP lead free solder bumped devices attached to organic chip carriers. Mold fill data for CSP type dimensions is included. Solder metrology data and yield information for fine pitch applications is summarized. Relevant process equipment technology and the unique requirements to run a high volume manufacturing C4NP process are reviewed. The paper also summarizes the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is provided by IBMs packaging operations at the Hudson Valley Research Park in East Fishkill, NY and Bromont, Quebec

Lead free solder bump manufacturing with IBM's C4NP process

More and more high-end microelectronic devices are being packaged by using solder bumps as the method of interconnection. The two main technologies used are flipchip in package (FCiP) and wafer level chip scale package (WLCSP). The main difference is that FCiP devices are placed on a substrate which then interconnects to the PC board (PCB). WLCSP devices connect directly onto the board. C4NP (C4-new process) is a novel solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). Mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost solution for both, fine-pitch FC in package as well as large pitch/large ball WLCSP bumping applications

C4NP - data for fine pitch to CSP flip chip solder bumping

To meet nature requirements for cost, size, weight and electrical performance, microelectronic packaging is moving from wire bonds to solder bumps as the preferred method of interconnection from the device to the chip carrier or card. Flip chip in package (FCiP) requires many small bumps on tight pitch whereas wafer level chip scale packaging (WLCSP) typically requires much larger solder bumps on a greater pitch. Electroplating, solder paste printing and the direct attach of preformed solder spheres are technologies commonly used in volume production. Each of these techniques has limitations in scaling from fine pitch FCiP to WLCSP. Electroplating is better suited to fine pitch, whereas solder paste printing and solder sphere attachment work well for coarser pitches. C4NP (controlled collapse chip connection new process) has proven to be suitable for this entire range of solder bump pitch. C4NP is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity/contact and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications. This paper summarizes the latest manufacturing and reliability data for high-end logic device packaging using 300mm wafers bumped with C4NP. This includes reliability data for C4NP lead free solder bumped devices attached to organic chip carriers. Mold fill data for CSP type dimensions is included. Solder metrology data and yield information for fine pitch applications is summarized. Relevant process equipment technology and the unique requirements to run a high volume manufacturing C4NP process are reviewed. The paper also summarizes the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is provided by IBMs packaging operations at the Hudson Valley Research Park in East Fishkill, NY and Bromont, Quebec.