Renee T. Mo

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at Lgate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12Å) for BE nFET devices to-date, consistent with simulations showing the need for ≪14Å Tinv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFETs fabricated with gate-first high thermal budget processing with thin Tinv (≪13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFETs into CMOS devices yielded large SRAM arrays.

On the integration of CMOS with hybrid crystal orientations

Design and integration issues have been investigated for the hybrid orientation technology (HOT), i.e. device isolation, epitaxy and dopant implantation. Ring oscillators using HOT CMOS have been demonstrated for the first time, with L/sub poly/ about 85nm and t/sub ox/=2.2nm, resulting in 21% improvement compared with control CMOS on (100) orientations.

Dual stress liner enhancement in hybrid orientation technology

Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown [110] bulk silicon. Stress induced by the nitride MOL liners results in mobility enhancement that depends on the designed orientation of the gate, in agreement with theory. Compressive stressed liner films are utilized to increase HOT PFET saturation current to 635 uA/um I/sub DSat/ at 100 nA/um I/sub OFF/ for V/sub DD/=1.0 V at a 45 nm gate length. The AC performance of a HOT ring oscillator shows 14% benefit from [110] silicon and an additional 8% benefit due to the compressive MOL film.

Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demonstrated in 45 nm ground-rules at 1V and 200nA/mum off current for nFETs and pFETs, at a Tinv of 14 and 15 respectively. The drive currents were achieved using a simplified high-k/metal gate integration scheme with embedded SiGe and dual stress liners (DSL) and without utilizing additional stress enhancers. Devices have been fabricated with Tinvs down to 12 and 10.5 demonstrating the scalability of this approach for 32 nm and beyond.

High-mobility High-Ge-Content Si 1−x Ge x -OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x∼ 0.7, scaled EOT∼8.5Å and ∼10nm fin width

We demonstrate scaled High-Ge-Content (HGC) SiGe-OI finFET with Ge up to 71%, using a CMOS-compatible approach. For the first time, aggressively scaled HGC relatively-tall fins with vertical sidewalls and sub-10nm widths have been demonstrated using an enhanced 3D-Ge-condensation technique. An improved Si-cap-free HK/MG process featuring optimized IL has been developed resulting in scaled EOT and impressive long channel SS=69mV/dec. The gate stack results in realization of enhancement-mode devices for Ge content ∼0.6. Moreover, long-channel mobility characteristics at scaled EOT as well as short-channel pMOS FinFETs with decent cut-off behavior and performance are demonstrated, for the first time. As a result, we report the highest HGC SiGe pMOS FinFET mobility of ∼300cm2/Vs at N inv =1013cm−2 at scaled EOT=0.85nm.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1-4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT ∼7Å and scaled dimensions down to sub-4nm fin widths

High-Ge-content (HGC) SiGe FinFETs in a “replacement High-K and metal-gate” (RMG) process flow and with aggressive EOT scaling are demonstrated, for the first time. HGC SiGe pMOS FinFETs with high-mobility, record-low RMG long-channel SS=66mV/dec and great short-channel characteristics down to L_G=21nm have been demonstrated. Gate stack and transport properties down to sub-4nm fin widths (W_FIN) have been also studied for the first time. We demonstrate excellent RMG mobility and reliability at aggressive EOT~7Å, and excellent μ_eff=220cm²/Vs at N_inv=10¹³ for fins with W_FIN~4nm, outperforming state-of-the-art devices at such dimensions and providing very promising results for FinFET scaling for future high-performance FinFET generations.

SiGe-on-insulator symmetric lateral bipolar transistors

We report the first demonstration of thin-base symmetric lateral NPN bipolar transistors built on 8-inch SiGe-on-insulator (SiGe-OI) wafers with CMOS-like process. Such devices achieve the same collector current as the SOI bipolar transistor at ~130 mV lower VBE from effective bandgap lowering, translating into lower voltage operation and power dissipation. Various techniques of Emitter engineering were studied and a novel partial HBT device structure was demonstrated with 3× reduction of hole injection into the emitter.

High performance and record subthreshold swing demonstration in scaled RMG SiGe FinFETs with high-Ge-content channels formed by 3D condensation and a novel gate stack process

We demonstrate scaled high-Ge-content (HGC) strained SiGe pMOS FinFETs with very high short channel (SC) performance using a Replacement High-K/Metal Gate (RMG) flow, for the first time. A novel RMG gate stack process was introduced to create Ge-free interface-layer (IL) with excellent reliability and sub-threshold swing (SS) as low as 62mV/dec, the best reported to date for Si-cap-free SiGe FinFETs. We also present some structural details of the gate stack, for the first time. Short channel characteristics of HGC SiGe FinFETs have also been studied for various fin widths. Compared to our earlier RMG work, improved I/I free process with ultra-thin spacers has led to considerable R<inf>on</inf> and R<inf>ext</inf> reduction. As a result, we have demonstrated very high SiGe performance with I<inf>on</inf>=0.45mA/μm at I<inf>off</inf>=100nA/μm at V<inf>dd</inf>=0.5V for L<inf>G</inf>=25nm, matching our record for gate-first SiGe FinFETs and outperforming the gate-first results at such LG.