Shigehito Saigusa

A 1.8GHz linear CMOS power amplifier with supply-path switching scheme for WCDMA/LTE applications

Low-cost CMOS PAs for mobile terminals have been a focus of attention in recent years. Self-contained, linear CMOS PAs are particularly attractive for smooth replacement of conventional compound semiconductor PA products. The main challenge concerning the linear CMOS PAs is to improve their power efficiency. Doherty PAs improve the average power efficiency by means of backoff efficiency boosting; however, their applicable carrier frequency range is narrow owing to the high-order output network. Supply modulation is another technique to improve the PA back-off efficiency. Although hybrid modulators have been studied for CMOS polar transmitters [1,2], none of them have satisfied full specs of modulation bandwidth and the output power for 4G cellular applications. The area overhead is also unacceptable for application to a self-contained linear PA. A class-G supply modulator relaxes the limitations by receiving external, discrete levels of supply voltages [3]. However, it still requires a costly extra DC-DC converter for multilevel supply voltages.

A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion

A series combining transformer(SCT)-based, watt-level 1.9 GHz linear CMOS power amplifier with an on-chip linearizer is demonstrated. Proposed compact, predistortion-based linearizer is embedded in the two-stage PA to compensate AM-PM distortion of the cascode power stages, and improve ACLR of 3GPP WCDMA uplink signal by 2.6 dB at 28.0 dBm output power. The designed interstage power distributor with one tuning inductor contributes to low-loss power supply for the driver stage and high common-mode stability of the whole PA. Moreover, a newly developed PVT variation- tolerant cascode biasing circuit guarantees highly accurate bias voltages in a wide supply voltage range from 2.5 V to 3.6 V. The test chip demonstrates maximum output power of 28.3 dBm at 1.95 GHz, satisfying 3GPP WCDMA spectrum mask with die area of 5.4 mm2.

A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique

A watt-level, fully integrated 1:1 Doherty power amplifier for 2.4 GHz band is demonstrated in 65 nm CMOS. Both high peak output power of +30.5 dBm and high PAE of 23% at 6 dB power back-off are achieved by the proposed compact output network. A newly introduced reliability enhancement technique for sub-PA prolongs time to failure by up to 75% as well. The PA satisfies IEEE 802.11b and 11g spectrum masks at output power levels of 25.5 and 21.5 dBm respectively, from supply voltage of 3.3 V.

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication

A fully-integrated single-chip CMOS transceiver with MAC and PHY for 60GHz proximity wireless communication is presented. A 60GHz wireless communication single-chip transceiver has not yet been reported due to large power consumption issues. However, by limiting the application to high-throughput proximity transmission, thermal issues arising in a single-chip have been overcome. A 2GHz broadband OFDM single-chip transceiver suffers from SNR degradation due to the reference clock (REFCLK) and baseband clock (BBCLK) spurs in RF/analog circuits. Low frequency spurs in the clock generator (CLKPLL) due to the mixing of the ADC/DAC sampling clock (SCLK) and other clocks such as REFCLK and BBCLK have been eliminated by careful frequency planning of those clocks. In addition to that, spur suppression in digital baseband and noise-tolerant RF/analog circuit designs are employed. The spurs have been successfully suppressed to less than -35dBc. The chip achieves a PHY data-rate of 2.35Gb/s and MAC throughput of 2.0Gb/s at a distance of 4cm. Power consumption is scalable to the throughput by the introduction of fast Sleep and Awake modes. The average power consumption at a throughput of 0.2Gb/s is reduced to 36% of that at 2.0Gb/s.

A digitally stabilized type-III PLL using ring VCO with 1.01ps rms integrated jitter in 65nm CMOS

The design of low-jitter VCO-based PLLs is quite challenging as high VCO control gain, KVCO, increases the phase noise contribution arising from the charge pump and loop filter. To resolve this problem, dual-tuning PLLs (DT-PLLs) have been studied [1-4]. The DT-PLL structure adds a narrow-bandwidth coarse (high-KVCO) path to the fine (low-KVCO) path consisting of a type-II PLL. The narrow-bandwidth analog filter in the coarse path plays an important role in preventing the charge pump and the loop filter from increasing the output jitter, while a wide-tuning range is maintained. Moreover, the coarse path adds another pole at origin to the fine path and transforms it from a type-II to type-III PLL [3-4]. Compared to a type-II PLL, owing to its boosted low-frequency loop gain, a type-III PLL can better suppress a low-frequency disturbance to the ring VCO, such as temperature drift. However, a type-III PLL has stability problems. To ensure sufficient phase margin (PM), a type-III PLL requires an extremely narrow-bandwidth (e.g. ~10-100Hz) analog filter in the coarse path or must make the KVCO of the fine path larger. The former requires a nano-Farad capacitor or a fairly complex design for shrinking the capacitance, while the latter way increases total jitter. This paper presents a digitally stabilized type-Ill PLL with a ring VCO. It employs a DT-PLL structure and improves its stability by composing the coarse path with a digital integrator and a digital-to-analog converter (DAC). It can set the Kvco of the fine path to 10MHz/V, which is 1000χ lower than that of the coarse path with a sufficient PM. For further in-band phase-noise reduction, the proposed type-Ill PLL adopts a sub-sampling PLL (SS-PLL) in its fine path [5], and achieves 1.01 psrms integrated jitter.

A 2.4 GHz CMOS Doherty power amplifier with dynamic biasing scheme

A watt-level, fully integrated 1:1 Doherty power amplifier with dynamic biasing scheme is demonstrated in 65 nm CMOS. The newly implemented dynamic biasing scheme for sub-PA solves the gain-linearity trade-off of the Doherty PA with enough back-off efficiency improvement, and protects the gate oxide of the sub-PA from over-voltage stress as well. The PA delivers 30.4 dBm of peak output power with maximum 6 points of PAE improvement compared with a class-B PA, and satisfies IEEE 802.11b and 11g spectrum masks at output power levels of 24.3 and 23.2 dBm, respectively, from supply voltage of 3.3 V.

A single-chip RF tuner / OFDM demodulator for mobile digital TV application

This paper presents the first published single-chip RF tuner / OFDM demodulator for a mobile digital TV application (1-segment broadcasting). To improve the minimum sensitivity, spurious signal suppression techniques are proposed. The single-chip RF tuner / OFDM demodulator using the proposed spurious signal suppression techniques is fabricated using 90nm CMOS technology and total die size is 3.26mm×3.26mm. By suppressing undesired spurious signals, the minimum sensitivity of −98.6dBm is achieved. The optimum current consumption is chosen for the RF tuner by using an adaptive control, the power consumption of the proposed single-chip receiver is only 60mW in medium-signal receiving mode.

A temperature variation tolerant 60 GHz Low Noise Amplifier with current compensated bias circuit

This paper presents a temperature variation tolerant 60 GHz Low Noise Amplifier (LNA) for mm-wave communication systems. The proposed temperature compensated bias circuit is utilized for the common source LNA. The temperature variation of S21 is 1.71dB in the temperature range from -20°C to 100°C, which is 47% lower than the value reported in previous work. The Figure of Merit (FoM) of the proposed LNA at 25°C is comparable to the top value of state-of-the-art work and FoM at 100°C is also comparable to those reported in the literature operated at room temperature.

A 1024-QAM capable WLAN receiver with −56.3 dB image rejection ratio using self-calibration technique

This paper presents a 1024-QAM OFDM signal capable WLAN receiver in 65 nm CMOS technology. Thermal noise-based IQ frequency-independent mismatch correction and IQ frequency-dependent mismatch correction with baseband loopback are proposed for the self-calibration in the receiver. By using proposed calibration method, neither received external signal nor RF loopback are necessary and the residual IQ mismatch of TXBB can be removed. The measured image rejection ratio of the self-calibration is −56.3 dB. The receiver achieves the extremely low EVM of −37.1 dB even with wide channel bandwidth of 80 MHz and has the ability to receive the 1024-QAM signal. The result indicates that the receiver is extendable for the 802.11ax compliant receiver that supports a higher density modulation scheme of MIMO.

A wide bandwidth analog front-end circuit for 60-GHz wireless communication receiver

This paper presents an analog front-end circuit for a 60-GHz wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224 mW Power consumption.