Hisakatsu Araki
Fujitsu
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Featured researches published by Hisakatsu Araki.
symposium on vlsi circuits | 1998
Shigetoshi Wakayama; Kohtaroh Gotoh; Miyoshi Saito; Hisakatsu Araki; Tsz-shing Cheung; Junji Ogawa; Hirotaka Tamura
We propose a fast row-cycle DRAM-core architecture, which employs temporal data storage buffers in the sense amplifier and pipelined row-address decoding. The temporal data storage buffers eliminated the restoring time and reduced the bit-line precharge time. The pipelined row-address decoding reduced the skew in its decoding operation. We confirmed a 10 ns row-access cycle time by SPICE simulations based on a 0.24 /spl mu/m DRAM technology.
Archive | 1998
Hirotaka Tamura; Hisakatsu Araki; Shigetoshi Wakayama; Kohtaroh Fujitsu Ltd Gotoh; J. Ogawa
Archive | 2002
Hirotaka Tamura; Miyoshi Saito; Kohtaroh Gotoh; Shigetoshi Wakayama; Junji Ogawa; Hisakatsu Araki; Tsz-shing Cheung
Archive | 2001
Hirotaka Tamura; Hisakatsu Araki; Shigetoshi Wakayama; Kohtaroh Gotoh; Junji Ogawa
Archive | 1998
Hisakatsu Araki; Kotaro Goto; Yasutaka Tamura; Shigetoshi Wakayama; 公太郎 後藤; 泰孝 田村; 繁俊 若山; 久勝 荒木
Archive | 1997
Hisakatsu Araki; Shisei Chiyou; Kotaro Goto; Junji Ogawa; Yoshihisa Saito; Yasutaka Tamura; Shigetoshi Wakayama; 淳二 小川; 公太郎 後藤; 泰孝 田村; 繁俊 若山; 久勝 荒木; 美寿 齋藤
Archive | 1997
Hirotaka Tamura; Miyoshi Saito; Kohtaroh Gotoh; Shigetoshi Wakayama; Junji Ogawa; Hisakatsu Araki; Tsz-shing Cheung
Archive | 1997
Hirotaka Tamura; Miyoshi Saito; Kohtaroh Gotoh; Shigetoshi Wakayama; Junji Ogawa; Hisakatsu Araki; Tsz-shing Cheung
Archive | 1998
Hirotaka Tamura; Hisakatsu Araki; Shigetoshi Wakayama; Kohtaroh Gotoh; Junji Ogawa
Archive | 1998
Hirotaka Tamura; Hisakatsu Araki; Shigetoshi Wakayama; Kohtaroh Gotoh; Junji Ogawa
