Tsz-shing Cheung

A 0.11 /spl mu/m CMOS clocked comparator for high-speed serial communications

A differential comparator targeted at receiving 40 Gb/s signals and operating off a single 1.2 V supply was designed and fabricated in 0.11 /spl mu/m CMOS. It comprises a front-end sampler and a regenerative stage with a clocked buffer to achieve a narrow aperture time and a high toggle rate. The regenerative stage output buffer employs an impedance modulation technique based on switching of feedback gain to reduce the reset time while keeping the effective gain high. We confirmed comparator operation with BER less than 10/sup -12/ up to 32 Gb/s at a toggle rate of 8 GHz.

10-ns row cycle DRAM using temporal data storage buffer architecture

We propose a fast row-cycle DRAM-core architecture, which employs temporal data storage buffers in the sense amplifier and pipelined row-address decoding. The temporal data storage buffers eliminated the restoring time and reduced the bit-line precharge time. The pipelined row-address decoding reduced the skew in its decoding operation. We confirmed a 10 ns row-access cycle time by SPICE simulations based on a 0.24 /spl mu/m DRAM technology.

A 24-Gb/s source-series terminated driver with inductor peaking in 28-nm CMOS

We designed and tested a 24-Gb/s source-series terminated (SST) driver in 28-nm CMOS. The driver is composed of four segments with different weights to achieve an adjustable tap-weight finite-impulse-response (FIR) filter. The driver consists of nine slices, each of which contains four driver units. Each driver unit has a minimum-sized output stage regardless of the tap weight to reduce the power consumption of the preceding pre-driver stages. Series inductors connected to the output terminal of the driver are used to form a π-network circuit to enhance the bandwidth. The driver consumes 27.8 mW off a 0.85-V single supply. The total output jitter is 14.9 ps, which includes an input jitter of 11.1 ps. The core area is 330 × 330 μm2 with bumps.