Koichiro Zaitsu

Nonvolatile Programmable Switch With Adjacently Integrated Flash Memory and CMOS Logic for Low-Power and High-Speed FPGA

Novel nonvolatile programmable switch for low-power and high-speed field-programmable gate array (FPGA) where flash memory is adjacently integrated to CMOS logic is demonstrated. The flash memory and the high-speed switching transistor (SwTr) are fabricated close to each other without deteriorating their respective performance. Furthermore, programming schemes to write and erase the flash memory are optimized so that the memory is successfully programmed without any damage to the SwTrs. Flash-based configuration memory in the nonvolatile programmable switch has only half the area of the conventional static random-access memory-based one, and it can be placed in each block in FPGA, enabling efficient power gating that offers low-power FPGA operation.

Flash-based nonvolatile programmable switch for low-power and high-speed FPGA by adjacent integration of MONOS/logic and novel programming scheme

Novel nonvolatile programmable switch for low-power and high-speed FPGA where MONOS flash is adjacently integrated to CMOS logic is demonstrated. The MONOS transistors (MTrs.) and low-voltage switching transistors (SwTrs.) are fabricated close to each other without deteriorating each performance. Furthermore, memory programming scheme is optimized to realize selective writing with no damage in the SwTrs. MONOS-based configuration memory has a half area of conventional SRAM, and it can be placed in each block in FPGA. That enables efficient power gating (PG) that offers low-power FPGA operation.

Novel Dynamic Reconfigurable FPGA based on Multi-Context Scheme Using One-Time Memory with Gate-Induced Permanent Path

We present a multi-context based dynamic reconfigurable FPGA (MC-DPGA) that is smaller than conventional FPGA. To mitigate the memory area, novel one-time programmable (OTP) memories based on standard CMOS transistors are employed to configuration memories. Since different terminals are used in programming and in reading unlike conventional OTP memories, it is simple to embed the configuration memories in logic circuits. We have estimated the mapping area using 10 benchmark circuits, and confirmed that the area of MC-DPGAs is reduced by 30 % on average.

High-density user-programmable logic array based on adjacent integration of pure-CMOS crossbar antifuse into logic CMOS circuits

Novel crossbar antifuse for high-density user programmable logic array (PLA) is presented. Circuit area reduction and routability increase of PLA are achieved by crossbar architecture based on pure-CMOS antifuse adjacently integrated into low-voltage and high-speed logic transistors. In addition, since our crossbar antifuse technique can be fabricated according to the standard design rule of advanced CMOS process, it is easy to implement our PLA as a user-customizable embedded logic in SoC. The logic density of our test chip in 65 nm process technology is 1835 lookup-tables (LUTs)/mm2, which is larger than any previous reports.

Standard CMOS Based One-Time Programmable Switches with Gate-Induced Permanent Source-Drain Path

Three-terminal one-time programmable switches using standard CMOS transistors are demonstrated. By gate-controlled programming, permanent conductive path is formed between the source and drain because of local breakdown in the PN junctions. Since different terminals are used between in programming and in reading, the proposed switch makes it easy to design the peripheral circuit. This method is applicable to standard CMOS devices and does not require any special manufacturing processes, which enables to realize the low-cost LSI with one-time programmable switches.