Mari Matsumoto

1200μm 2 Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application

In this work, because of the high-amplitude random noise at high frequency from the SiN MOSFET, we need only a single amplifier and A/D converter, and the amplifier area is decreased.

High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code

A high-speed random number generator (RNG) circuit based on magnetoresistive random-access memory (MRAM) using an error-correcting code (ECC) post processing circuit is presented. ECC post processing increases the quality of randomness by increasing the entropy of random number. { We experimentally show that a small error-correcting capability circuit is sufficient for this post processing. It is shown that the ECC post processing circuit powerfully improves the quality of randomness with minimum overhead, ending up with high-speed random number generation. We also show that coupling with a linear feedback shift resistor is effective for improving randomness

Nonvolatile Programmable Switch With Adjacently Integrated Flash Memory and CMOS Logic for Low-Power and High-Speed FPGA

Novel nonvolatile programmable switch for low-power and high-speed field-programmable gate array (FPGA) where flash memory is adjacently integrated to CMOS logic is demonstrated. The flash memory and the high-speed switching transistor (SwTr) are fabricated close to each other without deteriorating their respective performance. Furthermore, programming schemes to write and erase the flash memory are optimized so that the memory is successfully programmed without any damage to the SwTrs. Flash-based configuration memory in the nonvolatile programmable switch has only half the area of the conventional static random-access memory-based one, and it can be placed in each block in FPGA, enabling efficient power gating that offers low-power FPGA operation.

Flash-based nonvolatile programmable switch for low-power and high-speed FPGA by adjacent integration of MONOS/logic and novel programming scheme

Novel nonvolatile programmable switch for low-power and high-speed FPGA where MONOS flash is adjacently integrated to CMOS logic is demonstrated. The MONOS transistors (MTrs.) and low-voltage switching transistors (SwTrs.) are fabricated close to each other without deteriorating each performance. Furthermore, memory programming scheme is optimized to realize selective writing with no damage in the SwTrs. MONOS-based configuration memory has a half area of conventional SRAM, and it can be placed in each block in FPGA. That enables efficient power gating (PG) that offers low-power FPGA operation.

Non-Stoichiometric SixN Metal–Oxide–Semiconductor Field-Effect Transistor for Compact Random Number Generator with 0.3 Mbit/s Generation Rate

The demand for random numbers for security applications is increasing. A conventional random number generator using thermal noise can generate unpredictable high-quality random numbers, but the circuit is extremely large because of large amplifier circuit for a small thermal signal. On the other hand, a pseudo-random number generator is small but the quality of randomness is bad. For a small circuit and a high quality of randomness, we purpose a non-stoichiometric SixN metal–oxide–semiconductor field-effect transistor (MOSFET) noise source device. This device generates a very large noise signal without an amplifier circuit. As a result, it is shown that, utilizing a SiN MOSFET, we can attain a compact random number generator with a high generation rate near 1 Mbit/s, which is suitable for almost all security applications.

High-density user-programmable logic array based on adjacent integration of pure-CMOS crossbar antifuse into logic CMOS circuits

Novel crossbar antifuse for high-density user programmable logic array (PLA) is presented. Circuit area reduction and routability increase of PLA are achieved by crossbar architecture based on pure-CMOS antifuse adjacently integrated into low-voltage and high-speed logic transistors. In addition, since our crossbar antifuse technique can be fabricated according to the standard design rule of advanced CMOS process, it is easy to implement our PLA as a user-customizable embedded logic in SoC. The logic density of our test chip in 65 nm process technology is 1835 lookup-tables (LUTs)/mm2, which is larger than any previous reports.

Standard CMOS Based One-Time Programmable Switches with Gate-Induced Permanent Source-Drain Path

Three-terminal one-time programmable switches using standard CMOS transistors are demonstrated. By gate-controlled programming, permanent conductive path is formed between the source and drain because of local breakdown in the PN junctions. Since different terminals are used between in programming and in reading, the proposed switch makes it easy to design the peripheral circuit. This method is applicable to standard CMOS devices and does not require any special manufacturing processes, which enables to realize the low-cost LSI with one-time programmable switches.

Double Junction Tunnel Using Si Nanocrystalline Layer for Nonvolatile Memory Devices

A novel nonvolatile memory tunnel layer structure is proposed in which a Si nanocrystalline layer lies between double tunnel oxides. By Si nanocrystal size downscaling to 2 nm, the new double junction tunnel attains a remarkable 3×106 times retention improvement while keeping high-speed write/erase compared to single tunnel oxide. Based on Si nanocrystal size confirmation by transmission electron microscope (TEM), we show quantitatively that the advantage is due to Coulomb blockade and quantum confinement, and smaller Si nanocrystal will lead to greater improvement. We clarify a characteristic effect in double junction tunnel, tunnel penetration disappearance, which is extremely advantageous for nonvolatile memory applications and never occurs in other multilayer dielectrics structures. The double tunnel junction using Si nanocrystalline layer is very promising for future memory.