Koreaki Fujita
Mitsubishi
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Publication
Featured researches published by Koreaki Fujita.
IEEE Journal of Solid-state Circuits | 1996
Tadato Yamagata; Hirotoshi Sato; Koreaki Fujita; Yasumasa Nishimura; Kenji Anami
This paper describes a distributed globally replaceable redundancy (DGR) scheme which achieves a higher optimization of the trade-off between yield enhancement and chip area penalty. A newly developed yield simulator using the Monte Carlo method has estimated the effectiveness of the DGR scheme in a quantitative manner. The new redundancy scheme is expected to enhance the yield by several times compared with conventional redundancy in the early stages of production. The DGR scheme has been successfully implemented in an experimental 4 Mb SRAM with a 3.0% area overhead and an average redundancy usage efficiency of 61% has been obtained in repaired pass chips.
international solid-state circuits conference | 1991
Shuji Murakami; Koreaki Fujita; Motomu Ukita; Kazuhito Tsutsumi; Yasuo Inoue; Osamu Sakamoto; Motoi Ashida; Yasumasa Nishimura; Yoshio Kohno; Tadashi Nishimura; Kenji Anami
The authors describe a 21-mW 4-mB CMOS SRAM for the application of memory systems which operate on 3-V batteries. A low active power is achieved by novel circuit technologies. A thin-film transistor (TFT) load memory cell effectively reduces standby current to 0.4 mu A. A new multibit test circuit, which permits measurement of access time, is also introduced for a reduction of the test time. The authors describe the characteristics of the TFT memory cell and the improved memory cell design for stable cell operation. The 0.6- mu m process technology used to fabricate the 4-Mb SRAM and the chip performance are outlined. >
IEEE Journal of Solid-state Circuits | 1991
Hirotada Kuriyama; Toshihiko Hirose; Shuji Murakami; Tomohisa Wada; Koreaki Fujita; Yasumasa Nishimura; Kenji Anami
A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 mu m CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V. >
Archive | 1992
Koreaki Fujita; Masayuki Yamashita; Masamitsu Shimasaki
Archive | 1991
Koreaki Fujita; Shuji Murakami; Kenji Anami
Archive | 1995
Koreaki Fujita
Archive | 1992
Koreaki Fujita; Masayuki Yamashita; Masamitsu Shimasaki
Archive | 1987
Hiroshi Minami; Koreaki Fujita
Archive | 1993
Yoshiyuki Haraguchi; Koreaki Fujita; Kiyoyasu Akai
Archive | 1988
Hiroshi Minami; Koreaki Fujita