Shuji Murakami

A 20 ns 4 Mb CMOS SRAM with hierarchical word decoding architecture

A 20-ns, 4-Mb CMOS SRAM with both 4 M*1 and 1M*4 organizations and fabricated using a quadruple-polysilicon, double-metal, twin-well 0.6- mu m CMOS process technology is described. A word-decoding architecture and a sensitive sense amplifier, combined with an address transition detector (ATD) technique, realize high-speed, low-power operation. Because conventional divided-word-line (DWL) structure cannot realize the high-speed and low-power word decoding in megabit SRAMs, hierarchical word decoding (HWD) is utilized. The RAM has a fast address mode using the 16-b parallel data bus scheme.<<ETX>>

A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's

A single bitline cross-point cell activation (SCPA) architecture that reduces active power consumption and reduces the chip size of high-density SRAMs (static random access memories) is presented. The architecture enables the smallest column current possible without increasing the block division of the cell array. Since the decoder area is reduced due to less block division, the memory core can be smaller than with a conventional divided word line (DWL) structure. In the SCPA, the total active current is 15.9 mA, while in the conventional architecture it is 26.1 mA. In the SCPA, the memory cell size is equal to that in the conventional architecture; however, the number of local decoders is reduced from 64 to 8. Moreover, the number of GND lines is reduced because of a much smaller column current in SCPA. As a result, the area of the memory core is reduced by 10% in a 16-Mb SRAM. >

A multilevel QAM demodulator VLSI with wideband carrier recovery and dual equalizing mode

A 4-/16-/64-/256-QAM demodulator LSI with an all-digital carrier-recovery loop including a novel phase detector and a fractionally-/ symbol-spaced equalizer is described. The phase detector, deciding the transmitted symbol from received signal power, detects the phase error up to ±45° and enables the loop to internally eliminate the ±80 KHz carrier-frequency offset. The fractionally-spaced equalizer is implemented at the same clock rate as the symbol-spaced equalizer by only increasing the selectors and flip-flops, though the former theoretically requires a two times faster operation than the latter. An LSI operating at a symbol rate up to 8 MBaud is successfully implemented.

A 21-mW 4-Mb CMOS SRAM for battery operation

The authors describe a 21-mW 4-mB CMOS SRAM for the application of memory systems which operate on 3-V batteries. A low active power is achieved by novel circuit technologies. A thin-film transistor (TFT) load memory cell effectively reduces standby current to 0.4 mu A. A new multibit test circuit, which permits measurement of access time, is also introduced for a reduction of the test time. The authors describe the characteristics of the TFT memory cell and the improved memory cell design for stable cell operation. The 0.6- mu m process technology used to fabricate the 4-Mb SRAM and the chip performance are outlined. >

An 8 ns 4 Mb serial access memory

A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 mu m CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V. >

Improvement of soft-error rate in MOS SRAMs

Two techniques which reduce the alpha -particle-induced soft-error rate (SER) in MOS static RAMs (SRAMs) are described. The mechanism of the soft error is the high-resistive load memory cell is analyzed. It is found that the dependence of SER on the cycle time is caused by the potential drop in the high storage node, which is produced by the threshold current through the driver and access transistors in the memory cell. Improvement methods to suppress the subthreshold current are presented. One method utilizes high-threshold-voltage transistors in the memory cell. The other sets the selected word-line level lower than the supply voltage. Using these methods, the high storage node potential is kept at the supply voltage in spite of the small conductance of the load resistor. The effect is confirmed in 256 kbit CMOS SRAMs. The dependence of SER on the cycle time becomes negligible, and SER is improved by two orders of magnitude. >