Piotr Otfinowski

Measurements of Matching and Noise Performance of a Prototype Readout Chip in 40 nm CMOS Process for Hybrid Pixel Detectors

The paper presents a prototype integrated circuit built in a 40 nm CMOS process for readout of a hybrid pixel detector. The core of the IC constitutes a matrix of 18 ×24 pixels with the pixel size of 100 μm ×100 μm. The paper explains the functionality and the architecture of the IC, which is designed to operate in both the standard single photon counting mode and the single photon counting mode with interpixel communication to mitigate negative effects of charge sharing. This article focuses on the measurement results of the IC operating in the standard single photon counting mode. The measured ENC is 84e- rms (for the peaking time of 48 ns), the gain is 79.7 μV/e-, while the effective threshold dispersion is 21e- rms.

A bidirectional 64-channel neurochip for recording and stimulation neural network activity

We present the design and measurements of a novel 64 channel ASIC dedicated for recording and stimulation of neural network activity. Chip is designed in submicron CMOS 180nm technology, occupies 5×5 mm2 of silicon area, and consumes only 25 μW/channel. The low cut-off frequency can be tuned in the range 60 mHz-100 Hz while the mean high cut-off frequency is 4.7 kHz or 12 kHz. The recording channel voltage gain may be also changed. Mean measurement values show it may be either 139 V/V or 1100 V/V. The measured input referenced noise is 3.7 μV rms in band 100 Hz-12 kHz and 7.6 μV rms in band 3 Hz-12 kHz. For the input signals amplitude 1.5 mV, the THD is 1%. In order to satisfy requirements concerning spread of the main parameters of the multichannel system, each channel is equipped with the two corrections DACs. These allow to obtain voltage gain equal to 139 V/V with the standard deviation std = 0.67 V/V, and low cut-off frequency equal to 60 mHz with the std = 30 mHz only. Each channel is equipped additionally with a stimulation circuits allowing to generate stimulation pulses in the 125 nA-512 μA current range with 8-bit resolution. All ASIC configurations are set thanks to on-chip digital register controlled by the on-chip LVDS receivers.

Time and energy measuring front-end electronics for long silicon strip detectors readout

We report on the design of a self-triggered analog front-end readout electronics dedicated for signal detection from double-sided silicon microstrip sensors with capacitance at the order of tens pF (CDET ≈ 30 pF). The main requirements are: processing input pulses with the average rate of 150 kHz/channel, low power consumption and low noise at the same time. The single channel is built of two different parallel processing chains: the fast and slow. The fast path includes: a fast CR-RC shaper with the peaking time tp = 40 ns, a discriminator, a pulse stretcher and a time stamp latch. It is optimized to determine an input charge arrival time with resolution at the order of few ns. The slow path consists of: a slow shaper with the peaking time tp = 80 ns, a 5-bit flash ADC and a digital peak detector. This chain is dedicated for accurate energy measurement and it is optimized for low noise level. To protect against false noise-related hits coming from noisy fast processing path when the discrimination threshold is set low, the time-stamp validation circuit is used. Two prototype ASICs were implemented in UMC 180 nm CMOS technology: 8-channel AFE-XYTER and 128-channel STS-XYTER.

STS-XYTER, a high count-rate self-triggering silicon strip detector readout IC for high resolution time and energy measurements

We report on the design of a 128-channel ASIC named STS-XYTER (Silicon Tracking System - X - Y - Time -Energy Read-out) dedicated for signal detection from doublesided silicon microstrip sensors with high capacitance (CDET ≈ 30 pF). The STS-XYTER contains: 128 charge processing channels, a calibration unit, a biasing circuitry based on built-in band-gap reference source and a full digital back-end, which provides synchronization, control and sparsified fast data readout through four, 250 MHz DDR LVDS links based on the CBMnet protocol. The single readout channel uses two parallel signal processing paths (fast and slow) to handle an average rate of input pulses equals 150 kHz and provide an information about both interaction time and deposited charge with good noise performance and low power consumption (6.2 mW/channel) at the same time. The fast path, which is dedicated for determining the input charge arrival time, is built of: a fast shaper, a discriminator, a pulse stretcher and a time stamp latch. The slow path, which is optimized for a particle energy measurement, consists of a slow shaper, a 5-bit flash ADC and a digital peak detector.

Design and measurements of low power multichannel chip for recording and stimulation of neural activity

A 64-channel Neuro-Stimulation-Recording chip named NRS64 for neural activity measurements has been designed and tested. The NRS64 occupies 5×5 mm2 of silicon area and consumes only 25 μW/channel. A low cut-off frequency can be tuned in the 60 mHz - 100 Hz range while a high cut-off frequency can be set to 4.7 kHz or 12 kHz. A voltage gain can be set to 139 V/V or 1100 V/V. A measured input referenced noise is 3.7 μV rms in 100 Hz - 12 kHz band and 7.6 μV rms in 3 Hz - 12 kHz band. A digital correction is used in each channel to tune the low cut-off frequency and offset voltage. Each channel is equipped additionally with a stimulation circuit with an artifact cancellation circuit. The stimulation circuit can be set with 8-bit resolution in six different ranges from 500 nA - 512 μA range.

Noise optimization of the time and energy measuring ASIC for silicon tracking system

This paper presents multi-objective optimization of a front-end electronics implemented in multichannel integrated circuit for silicon sensors readout in the Silicon Tracking System in the CBM experiment at the FAIR center. We present the optimization towards low-power (<; 8 mW/channel) and low-noise while keeping the channel pitch of 58 μm and minimum number of external components required for the circuits operation. Detailed study of the system noise (equivalent noise charge) with respect to a realistic model of the detector and interconnecting kapton microcable as well as realistic models of decoupling capacitors, wire-bonds and on-chip power distribution network are included.

Comparison of allocation algorithms for unambiguous registration of hits in presence of charge sharing in pixel detectors

Charge sharing is the fractional collection of the charge cloud generated in a detector by two or more adjacent pixels. It may lead to excessive or inefficient registration of hits comparing to the number of impinging photons depending on how discrimination thresholds are set in typical photon counting pixel detector. The problems are particularly exposed for fine pixel sizes and/or for thick planar detectors. Presence of charge sharing is one of the limiting factors that discourages decreasing sizes of pixels in photon counting mode X-ray radiation imaging systems. Currently, a few different approaches tackling with the charge sharing problem exist (e.g. Medipix3RX, PIXIE, miniVIPIC or PIX45). The general idea is, first, to reconstruct the entire signal from adjacent pixels and, secondly, to allocate the hit to a single pixel. This paper focuses on the latter part of the process, i.e. on a comparison of how different hit allocation algorithms affect the spatial accuracy and false registration vs. missed hit probability. Different hit allocation algorithms were simulated, including standard photon counting (no full signal reconstruction) and the C8P1 algorithm. Also, a novel approach, based on a detection of patterns, with significantly limited analog signal processing, was proposed and characterized.

Flash ADCs for multichannel integrated systems in submicron technology

Multichannel readout systems for pixel or strip detectors often need a pulse amplitude measurement. For this purpose different kind of ADCs are used. For many applications the resolution of 4-6 bits is sufficient and the most important limitations are the circuit area, power consumption and fast signal processing. Such applications favor simplicity in choice of the architecture. This paper focuses solely on the flash ADCs with limited resolution, small area and conversion rates of few megasamples per second. The reduction of the converters area is beneficial in terms of speed and power consumption. However, it results in more pronounced mismatch effects, increased comparator threshold voltage variations and can lead to serious resolution degradation. The aim of this paper is to find the optimal solution for comparator offset voltage compensation in flash ADCs. This paper presents a comparison and a summary of the efficiency of different techniques, in terms of area, power consumption.

Asynchronous Approximation of a Center of Gravity for Pixel Detectors’ Readout Circuits

This paper presents an implementation of asynchronous approximation of a center of gravity of a binary object on a focal plane of a pixel detector. The direct field of its application is dealing with charge sharing in processing of signals from semiconductor X-ray hybrid pixel detectors. The developed algorithm is called the center of gravity in a temporal object (COGITO), standing for approximation of a geometrical COGITO that is a charge cloud sampled by a pixel detector. Its operation resembles image processing for finding a center of gravity of a binary object in an image. The presented circuitry operates entirely in the digital domain—the analog pixel front end is not included. Thus, this paper does not show a complete, self-consistent solution to X-ray or particle detectors. The key details of the concept and its implementation, followed by measurements obtained with a test chip designed in a 55-nm CMOS process, are presented. The algorithm can deal with arbitrarily large objects and allocation of a hit to a single pixel can be achieved in a few tens of nanoseconds.

Algorithms for elimination of charge sharing effects in single photon counting pixel detectors

This paper presents an analyze of various hit allocation algorithms for pixel readout circuits, which aim to compensate the charge sharing effect. A comprehensive pixel readout circuit model, which allows to measure the missed/false hit probability and hit allocation accuracy is described in detail. The presented simulation results compare the performance of existing algorithms in comparison with the novel solution, based on pattern recognition.