Kuan-Fu Chen

Source/Drain dopant concentration induced reliability issues in charge trapping NAND flash cells

Source/Drain (S/D) dopant concentration related reliability issues including erase speed degradation, sub-threshold swing (SS) increase, and program/erase (P/E) cycling induced low threshold voltage (VT) state drift and on-state current (ION) reduction are carefully examined in charge trapping (CT) NAND flash memories. Residual charges above S/D junctions has been identified as a dominant factor and cell performances are greatly improved with increasing S/D dosages. Moreover, a new program disturbance behavior, which possibly originates from junction leakage or breakdown induced hot carriers injection, is observed. Simulation results confirm that a high lateral junction field occurs at a program-disturbed cell once its S/D is fully depleted. Although optimizing S/D dosage can ease this situation, it is still a possible obstacle for further device scaling.

A novel BE-SONOS NAND Flash using non-cut trapping layer with superb reliability

This work presents superb chip-level reliability of a BE-SONOS charge trapping NAND fabricated in both 75nm and 38nm half-pitches. Without any error correction (ECC) >100K P/E cycling endurance for SLC and >3K endurance for MLC are obtained using a novel non-cut SiN trapping layer. Key process integration strategies are discussed, including barrier and trapping layer engineering, p-well and junction doping optimization, gate-etching profile, and SSL/GSL processing. In addition to the overall good performance in programming/erasing and reliability, the non-cut SiN also demonstrated charge retention without any lateral spread - contrary to common misperception of charge migration in SiN [1,2]. We believe this is the first time the reliability and performance of a charge trapping NAND chip are demonstrated to match or surpass those for FG NAND.

Study of electron and hole injection statistics of BE-SONOS NAND Flash

The electron and hole injection statistics of BE-SONOS NAND Flash is studied for the first time using a 75 nm charge-trapping NAND Flash test chip. By using the incremental step pulse programming (ISPP) method the impact of device variations are minimized and the electron number ( N ) fluctuation can be identified. We find that both electron and hole injection statistics well follow the Poisson statistics ( Sigma ∞ √N, where Sigma corresponds to the distribution width). However, due to the 3D fringing field effect the small transistors require more charge injection to obtain the same memory window, and this reduces the proportional factor of Sigma. We also found that the hole injection distribution is slightly broader than the electron injection, and can be explained by the lower charge centroid in nitride which leads to the larger proportional factor. Based on these results, we can also simulate the distribution for various technology nodes.

A NAND-type Flash Memory Using Impact Ionization Generated Substrate Hot Electron Programming (≫20MB/sec) and Hot Hole Erasing

A new method to program and erase NAND devices without using high voltage Fowler-Nordheim (FN) stressing is investigated. Impact Ionization generated substrate Hot Electron (IIHE) and Band to Band tunneling Hot Hole (BBHH) are proposed for SONOS-type NAND flash memory application. Both junctions are biased with the same voltage to perform double-side-charge-injection without lateral electrical field induced current. A novel divided bit line architecture is introduced to achieve this operation. Fast program and erase speed of < 100mus is achieved. Good 10 K cycling endurance and high temperature data retention are demonstrated. IIHE/BBHH for floating gate memory and body-tied FinFET-type SONOS are also demonstrated.

Chip-level reliability study of barrier engineered (BE) floating gate (FG) Flash memory devices

Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a large-density array (1Mb) was studied to provide chip-level reliability understandings. Finally, these results are compared with barrier engineered charge-trapping (CT) devices. Our results suggest that BE FG device is not promising in terms of serious reliability degradation and tail bits. Moreover, the speed enhancement is not better than using the conventional gate-coupling ratio (GCR) improvement or tunnel oxide scaling. On the other hand, CT devices do not have GCR and it need BE tunneling barrier to solve the erase and retention dilemma. We also prove that BE-SONOS device is immune to tail bits due to the nature of discrete trapped charge storage.

Investigation of Geometric Effect Impact on SONOS Memory in a NAND Array Structure

Geometric effects on program/erase speeds, endurance, and charge retention of polysilicon-oxide-nitride-oxide-silicon-type memories are investigated with various structures, including Flash cells, capacitors, and NAND array strings of different dimensions. NAND strings with common word-lines or/and bit-lines were employed to characterize the Lg and W effect on device performance, which builds up the capability to extrapolate the cell properties of various dimensions. For a charge trapping storage device, it suggests that the evaluation carried out on a large-area device always leads to a conclusion more optimistic than the cell inside array of a real product in all aspects. In addition, a numerical model is proposed to elucidate the observed phenomena from a statistical viewpoint.