Kwang-jin Moon

Investigation of Chemical Vapor Deposition (CVD)-Derived Cobalt Silicidation for the Improvement of Contact Resistance

The improved contact resistance was obtained by the new barrier metal scheme such as CVD-Co/Ti/TiN process in the level of about half of that from CVD-Ti/TiN process. And the mechanism of contact silicidation of CVD-Co/Ti/TiN was investigated. Because Co silicide may prohibit the Si diffusion into Ti silicide and Si recess during TiCl4-based CVD-Ti process, and the inertness of Co silicide to the dopants, the improved contact resistance with uniform silicide morphology was obtained. Therefore, CVD-Co/Ti/TiN contact silicide process can be regarded as the next generation contact silicidation process.

Annealing process and structural considerations in controlling extrusion-type defects Cu TSV

Stresses induced by the large volume of Cu in Through Silicon Vias (TSV) can result in global/local Cu extrusion which may affect reliability in 3D chip stacking technologies beyond the 28 nm node for high performance mobile devices. In this work, TSV structural factors that can influence extrusion post via filling are studied. In addition, the impact of the electroplating chemistry and annealing schemes on local extrusion type defect formation in TSVs are also studied.

Properties of isolation liner and electrical characteristics of high aspect ratio TSV in 3D stacking technology

As semiconductor performance improvements through device scale-down becomes more difficult, 3D chip stacking technology with TSVs (Through Silicon Via) is becoming an increasingly attractive solution to achieve higher system performances by way of higher bandwidth, smaller form factor and lower power consumption. Such increase in performance using TSV aided 3D chip stacking technology applies not only to homogenous chip stacking but to heterogeneous chip stacking (e.g. memory device on logic) as well, making it ideal for such applications in high performance mobile devices.

Comparison of PECVD-WN/sub x/ and CVD-TiN films for the upper electrode of Ta/sub 2/O/sub 5/ capacitors

The electrical characteristics of PECVD-WN/sub x/ and CVD-TiN films as the upper electrode for Ta/sub 2/O/sub 5/ capacitors were compared in a 3D stack structure. In terms of step coverage, CVD-TiN shows excellent results of about 90% at the stack structure corner, but PECVD-WN/sub x/ only reaches about 50%. However, WN/sub x/ electrodes at even 100 /spl Aring/-thickness exhibit equivalent capacitance and leakage current when compared with 150 /spl Aring/-thick CVD-TiN electrodes. It is demonstrated that both PECVD-WN/sub x/ and CVD-TiN are good candidates for the upper electrodes of Ta/sub 2/O/sub 5/ capacitors for ULSI DRAMs.

CVD-cobalt for the next generation of source/drain salicidation and contact silicidation in novel MOS device structures with complex shape

A novel CVD-cobalt process which enables a uniform salicidation even in novel MOS device structures with complex shape is developed for the first time. With CVD-cobalt salicidation, identical values of low sheet resistance can be realized on actives and gates regardless of the surrounding geometry, due to its excellent conformality. In addition, a low contact resistance can be obtained in small metal/active contacts even with high post thermal budget when CVD-Co is applied as an ohmic layer due to its conformality and inertness with the dopants. CVD-cobalt is a needed and suitable solution for the salicidation and silicidation of not only the continuously scaling conventional CMOS, but also the emerging next generation of devices with complex shapes and structures such as vertical and 3D FET.

Investigation of CVD-Co Silicidation for the Improvement of Contact Resistance

In present, TiCl4-based CVD-Ti/TiN process is widely used to make a TiSi2 ohmic layer in about sub-100nm contacts. But TiCl4 based CVD-Ti/TiN process has some problems such as reactivity of TiSi2 with dopant and rapidly increased contact resistance at small contact CDs. These problems of TiSi2 have limited the implementation and extension of the CVD-Ti./TiN barrier metal process. A novel barrier metal process has been needed for achieving low BL/n+ and BL/p+ contact resistances in the next generation devices with sub-100nm. One of the solutions for these problems is the change of ohmic material from TiSi2 to CoSi2 which has inert characteristics with the dopants for contact ohmic layer. Therefore, CVD-Co process can be a adequate alternative to CVD-Ti process in the development of next generation MOS devices. Recently, Kang et al. have reported that the usefulness of CVD-Co process using CCTBA precursor which has a good step coverage, and which can be also extended to the silicide in 110nm contacts for achieving low contact resistances. In this paper, the results of sub-100nm DC contact resistances with CVD-Co silicide are reported. we studied the reason of the degree of increase of Rc with decreasing contact size was lower with CVD-Co/Ti/TiN at small contacts compared to CVD-Ti/TiN. The mechanism responsible for Cobalt silicidation from CCTBA based CVD-Co in small DC was suggested by analysis of phase transformation and morphology of Co and Ti silicide.