Kwang-Yeob Lee

Wavelet-based vehicle tracking for automatic traffic surveillance

A system for wavelet-based vehicle tracking for automatic traffic surveillance is proposed. In order to meet real-time requirements, we use adaptive thresholding and a wavelet-based neural network (NN), which achieves low computational complexity, accuracy of localization, and noise robustness has been considered for vehicle tracking. The proposed system consists of three steps: moving region extraction, vehicle recognition and vehicle tracking. First, moving regions are extracted by performing a frame difference analysis on two consecutive frames using adaptive thresholding. Second, the wavelet-based NN is used for recognizing the vehicles in the extracted moving regions. The wavelet transform is adopted to decompose an image and a particular frequency band is selected for input of the NN for vehicle recognition. Third, vehicles are tracked by using position coordinates and wavelet features difference values for correspondence in recognized vehicle regions. Experimental results of the proposed system can be useful for a traffic surveillance system.

An adaptive road ROI determination algorithm for lane detection

Road conditions can provide important information for driving safety in driving assistance system. The input images usually include unnecessary information and road conditions need to be analyzed only in a region of interest (ROI) to reduce the amount of computation. In this paper, a vision-based road ROI determination algorithm is proposed to detect the road region using the positional information of a vanishing point and line segments. The line segments are detected using Hough Transform. The road ROI can be determined automatically and adaptively in every frame. The proposed method is applied to various video images from black boxes, and is verified to be robust.

Design of multi-core rasterizer for parallel processing

As resolution for displays is recently more and more increasing, the amount of data and calculation that graphic hardware needs to process are also increasing. Especially the amount of data processing by Rasterizer is rapidly increasing. This paper used an algorism using coordinates in center of gravity and area for triangle instead of using bilinear algorism [1] used by conventional interpolation, which is to make it easier for parallel processing by Rasterizer. This paper implemented designed Rasterizer under FPGA environment and compared it with conventional Rasterizer and verified it. This Rasterizer is proved to have approximately 50% higher performance compared to conventional one.

An implementation of the real-time panoramic image stitching using ORB and PROSAC

This paper proposes panoramic image stitching that operates in real time by applying ORB algorithm and PROSAC algorithm to the corresponding search phase in the panoramic image stitching. The conventional panoramic image stitching uses SURF or SIFT algorithm to detect feature points and RANSAC algorithm to remove outliers. However, SIFT or SURF algorithm requires a complicated operation, and RANSAC algorithm poses a difficulty of real-time processing since the processing time is in proportion to the accuracy due to its randomness. In this paper, the processing time is improved by applying ORB algorithm that reduces the amount of operation and PROSAC algorithm that shortens the operation time through non-randomness. The proposed method, which was implemented on an ORDROID-X2 board, showed an improvement of about 77% in the processing time compared to the conventional method to which SURF is applied.

FPGA based implementation of FAST and BRIEF algorithm for object recognition

In this paper, we implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per clock.

A hierarchical tiling algorithm for tile based rendering with Global Scratch Counter under multi core environment

As mobile computing technologies are developed, multi-core processors are introduced to the mobile devices. Multi-core, multi-thread systems require parallel processing software. In this paper, we propose an effective method of tile based rendering for a multi-core based GP-GPU environment.[1] A tile based rendering technique is adopted to reduce an amount of data transfer between the processor and external memory for resource-limited mobile environment.[2] The proposed algorithm is parallelized for multi-core environment with Global Scratch Counters. Tiling performance is also improved using hierarchical tiling technique.

Design of a fully programmable shader processor for low power mobile devices

In this paper, we propose a novel architecture of a general graphics shader processor without a dedicated hardware. Recently, mobile devices require the high performance graphics processor as well as the small size and low power. The proposed shader processor is a GP-GPU (General-Purpose computing on Graphics Processing Units) to execute the whole OpenGL ES 2.0 graphics pipeline by using shader instructions. It does not require the separate dedicate H/W such as rasterization on this fully programmable capability. The fully programmable 3D graphics shader processor can reduce much of the graphics hardware. The chip size of the designed shader processor is reduced less than 60% in comparison with previous processors.

The Design of Bi-CMOS LVDS Output Buffer with ESD Protection Circuit Using 90nm CMOS Technology

This paper presents the design of novel LVDS (Low-Voltage-Differential-Signaling) output buffer for Gb/sper-pin operation using 90 nm CMOS technology. The proposed LVDS driver is designed to reduce chip area, using a novel bipolar transistor switch. The proposed LVDS transmitter is operated at 1.8 V low-power supply. Its maximum data rate is 2.8 Gb/s approximately. Also, the new structural ESD (Electro-Static Discharge) protection device is designed to improve the proposed LVDS drivers ESD protection performance. The proposed device can reduce latch-up phenomenon in normal operating condition. In the measurement result, the proposed ESD clamp has trigger voltage of 3.7 V and holding voltage of 2.3 V. The robustness of the LVDS driver with proposed ESD protection has measured to about 2kV (IEC61000-4-2).

Electrical characteristics of novel ESD protection devices for I/O and power clamp

This paper presents a novel silicon controlled rectifier (SCR)-based (Electrostatic Discharge) ESD protection devices for I/O clamp and power clamp. The proposed ESD protection devices has a high holding voltage and a low tigger voltage characteristic than conventional SCR. These characteristics enable to latch-up immune under normal operating conditions as well as superior full chip ESD protection. Also, the propsed devices can provide area efficiency in comparison to conventional (Gate Grounded NMOS) GGNMOS. The propsed devices are fabricated by using 0.35um BCD (Bipolar-CMOS-DMOS) technology. From the experimental results, the device for Input/Output (I/O) clamp has a trigger voltage of 6.5V, 7.7V and 8.1V with the LG1 of 0.5um, 0.8um and 1um, respectively. And the device for power clamp has a holding voltage of 8V, 10V and 11.3V with the D1 of 4.5um, 5.5um and 7um. Also, the device for I/O clamp has trigger voltage of 7.8V to 8.9V with the gate length (LG1) of 0.5um, 0.8um and 1.0um. Moreover, The proposed devices have high ESD robustness.

A Design of Multi-threaded Shader Processor with Dual-Phase Pipeline Architecture

In this paper, Dual-Phase pipeline architecture and variable length instructions of a shader processor are proposed. The Dual-Phase pipeline architecture achieves a performance of dual core using a single core, and a parallelism of GP-GPU to accelerate graphic operations. For simplifying hardware, the register optimization is proposed. The variable length instructions are designed for efficient executions with less memory. Various pipeline hazards are resolved by a multi-threaded method. The proposed processor supports OpenGL ES 2.0. It has a size of 0.13Mlogic and shows the performance of 16.6MVertices/s, and 33.3MPixels/s