Kyeong-tae Kim

8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology

For the first time, 8 Gb multi-level cell (MLC) NAND flash memory with 63 nm design rule is developed for mass storage applications. Its unit cell size is 0.0164 /spl mu/m/sup 2/, the smallest ever reported. ArF lithography with off-axis illumination (OAI) was employed for critical layers. In addition, self-aligned floating poly-silicon gate (SAP), tungsten gate with an optimized re-oxidation process, oxide spacer and tungsten bit-line (BL) with low resistance were implemented.

Micro villus patterning (MVP) technology for 256 Mb DRAM stack cell

Micro villus patterning (MVP) technology which delivers the maximized cell capacitance is discussed. The key feature of the MVP technology is the formation of a hemispherical grain (HSG) archipelago and its transference to the underlayered oxide. The HSG archipelago pattern is produced on the oxide layer, and, by using that pattern as an etch mask, the oxide archipelago pattern is again transferred to the storage poly for the formation of villus bars by anisotropic dry etch. After the etching process, the oxide etch mask pattern is stripped away by using oxide wet etchant, so that additional Fin undercut structure is achieved underneath the main body. The main body of the storage electrode can be formed by single deposition and etch process, so that the storage electrode structure is strong enough to maintain its physical stability in spite of the complication of its shape. A 256-Mb DRAM-cell size of 0.6 approximately 0.8 mu m/sup 2/ having more than 30 fF of cell capacitance with a stack structure, has been realized.<<ETX>>

Tungsten silicide/titanium nitride compound gate for submicron CMOSFET

Experimental results are presented for a WSi2/TiN compound-gate MOSFET with a near-midgap work function ranging from 4.63 to 4.75 eV and low resistivity. Sheet resistances of the compound gate and the conventional n+ gate with and without the interconnection layer are studied, and it is shown that the compound gate materials are an adequate interconnection layer. When positive bias is applied to the gate, the tunneling current of a compound-gate MOS is similar to that of an n+-poly-gate MOS with and without interconnection layer. This is because electrons are tunneling through the oxide from the silicon substrate to the gate, so that the barrier height is defined dominantly by the oxide barrier from the silicon substrate

A novel 4.6F/sup 2/ NOR cell technology with lightly doped source (LDS) junction for high density flash memories

We have reported a 4.6F/sup 2/ NOR cell with a gate length of 0.3 /spl mu/m. The lightly doped source (LDS) junction is adopted to extend the effective channel length. The word line and source line pitch are significantly decreased with the self-aligned contact processing and W-pad source interconnection. Moreover, the LDS NOR cell shows the improved retention capability and the reduced oxide trapping.

A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-μm single-gate low-power SRAM device

A new double offset-implanted (DOI) technology, which can effectively suppress the gate-induced drain-leakage (GIDL) current of buried-channel PMOS transistor in small-size CMOS devices, is proposed and developed with a 0.12-/spl mu/m single-gate low-power SRAM device. The DOI scheme is characterized by the usage of the silicon nitride etch-stopper for the formation of borderless W-contact as offset spacer without supplementing auxiliary processes at p+ source/drain (S/D) implantation process after the n+ S/D one. It is assured that the DOI technology makes the gate-to-S/D overlap controllable, so that the GIDL current of PMOS transistor can remarkably be reduced. Furthermore, the enhancement of CMOS transistor performance was possible by reducing the sidewall reoxidation thickness of the gate-poly Si and optimizing the implantation conditions with this technology.

A novel 6.4 /spl mu/m/sup 2/ full-CMOS SRAM cell with aspect ratio of 0.63 in a high-performance 0.25 /spl mu/m-generation CMOS technology

Summary form only given. A unique 6.4 /spl mu/m/sup 2/ 6Tr. SRAM cell has been developed using an advanced CMOS technology implemented in 0.25 /spl mu/m design rule for high density and high speed applications. Very small aspect ratio of 0.63 has been achieved for the cell design. Special features in the layout are parallel active regions and orthogonal gate electrodes, all bar shape. Stable cell operation has been obtained at 0.5 V.

Effect of low-k dielectric material on 63nm MLC (multi-level cell) NAND flash cell arrays

We investigate the effect of applying oxide spacer into MLC NAND flash memory with 63nm design rule. The oxide spacer is effective on reducing cell to cell coupling with its low-k dielectric constant. The uniform cell V/sub th/ distribution of 0.6V fulfilling the MLC operation is obtained while maintaining fast programming speed and sufficient cell current.

Characteristics of Cell Latch and Leakage Current at Standby State in 6-T Low-Power Static Random Access Memory (SRAM) Device

The standby current at device off-state is investigated against the measuring mode in 6-T and low-power static random access memory (SRAM) device with short gate length of 0.12 µm and high density of 32 M-bit. It can be found that there is the difference of the standby currents between initial and D0 modes and this discrepancy in the standby current is closely related to the leakage current of cell n-type metal-oxide semiconductor field-effect transistor (NMOSFET), especially pull-down transistor. This discrepancy in the standby currents among the measuring modes can be explained with the characteristic of the cell latch using its dependence on the leakage current of pull-down transistor and it will be shown that the cell spontaneously moves to minimize the standby current.

Effects of gate notching profile defect on performance characteristics of short-channel NMOSFET with channel length of 0.12 μm

In this letter, we report the effects of gate notching on the performance characteristics of short-channel NMOS transistor with the gate oxide thickness of 32 /spl Aring/. The significant gate-notching defect into channel region brings about the serious degradation of such transistor performances as transconductance (G/sub m/) characteristic and subthreshold swing (S/sub t/), resulting in increases of threshold voltage (V/sub TH/) and leakage current (I/sub OFF/) and the considerable reduction of drive current (I/sub ON/). We will suggest the local thickening of gate oxide as a main mechanism of its effects and show that lack of gate-to-source/drain extension (SDE) overlap may be an additional reason for the degradation of I/sub ON/ with increasing the notch depth.