Yun-Seung Shin

Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers

Nano scale body-tied FinFETs have been firstly fabricated. They have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 60 nm. This Omega MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I/sub SUB//I/sub D/ than planar type DRAM cell transistors.

Non-volatile memory technologies for beyond 2010

The development of Flash memory technology over the past decade has been one of the driving forces behind the tremendous growth in digital consumer applications, such as digital cameras, handheld music players and mobile phones. NAND Flash has been leading the way from 16Mb in 1994 to 4Gb today. This paper discusses the impact of continuous advances in NAND Flash technology on consumer applications and also reviews technical challenges to the further scaling of NAND and NOR Flash memories, while considering the possibility of other nonvolatile memory technologies for high density nonvolatile data storage beyond 2010.

Low power operating bipolar TMO ReRAM for sub 10 nm era

The bottle neck of ReRAM (Resistive RAM) for post-NAND storage application is high operational current [1,2]. Herein, we report a method to acquire low operational currents from a hetero structure ReRAM (AlOx/TiOx). The mechanism study of the hetero structure ReRAM reveals that the AlOx layer as a tunnel barrier is critical for switching, and thus switching parameters are governed by the properties of the AlOx layer. By tuning tunnel oxide properties along with adopting 5 nm sized “Dash BE” [3], operational currents of ≤ 10 µA have been achieved from this hetero structure device.

A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture

This paper presents a hybrid-type TCAM architecture which can utilize the benefits of both NOR and NAND-type TCAM cells: high speed and low power. A hidden bank selection scheme is proposed to activate limited amount of cells during the search operation avoiding additional timing penalty. Match fine repeaters and sub-match fine scheme are used for fast NAND search operation. A test chip with 144-kb TCAM capacity is implemented using 0.1-/spl mu/m 1.2-V CMOS process to verify the proposed schemes. It shows 2.2 ns of match evaluation time on a 144-bit data search with 0.7 fJ/bit/search energy efficiency.

Highly manufacturable process technology for reliable 256 Mbit and 1 Gbit DRAMs

Ta/sub 2/O/sub 5/ dielectric on poly-Si cylinder capacitors, chemical-mechanical polishing (CMP) planarization, pure W bit-line, and Al reflow were integrated into a highly manufacturable DRAM process technology. This technology provided larger process margin, higher reliability, and better design flexibility. In addition, the critical steps of the new process has been reduced by 25% of those of the conventional process. The manufacturability of the technology has been proven by applying it to 16 Mbit density DRAMs with 256 Mbit design rule (0.28 /spl mu/m).<<ETX>>

Stress minimization in deep sub-micron full CMOS devices by using an optimized combination of the trench filling CVD oxides

We have found that the defect generation which is induced by the mechanical stress during the densification, depends on the ratio of the trench filling material composed of the TEOS-O/sub 3/ based CVD oxide with tensile stress and the plasma enhanced CVD oxide with compressive stress. The lower as-deposited stress is, the lower the maximum stress during the densification is. This stress level is proportional to the defect density which is generated in fabricating MOSFETs with Shallow Trench Isolation (STI). In order to achieve devices without a defect, it is important to minimize as-deposited stress level by optimizing the ratio of the trench filling CVD oxides.

On-axis scheme and novel MTJ structure for sub-30nm Gb density STT-MRAM

Feasibility of STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) as next generation non-volatile memory has been tested for the replacement of DRAM and NOR Flash. For competition with DRAM, STT-MRAM unit cell size should be reduced to 6 ∼ 8F2 and switching current density is required to be less than 1 MA/cm2. Here, we report that the cell characteristics of on-axis STT-MRAM with 6 ∼ 8F2 are similar to those of off-axis STT-MRAM with 12 ∼ 16F2. In addition, we suggest a novel MTJ (Magnetic Tunnel Junction) with the operation current density of 0.8 MA/cm2. These results open a way to scale STT-MRAM down to sub- 30 nm technology node using present technology. By further material engineering of ferromagnetic electrode and MTJ structure design, the usage of present technology could be extended down to sub-20 nm node.

An experimental 16-Mbit DRAM with reduced peak-current noise

An experimental 16-Mbit CMOS DRAM with die size of 8.52 X18.4 mm2 has been developed. A trenched and saddled stack capacitor (TSSC) cell was invented, and storage capacitance of 30fF was obtained in a cell size of 1.65 x 3.339 ?spl mu/m2. Peak-current noise on the power buses during the sense-amplifier latching is suppressed by distributing large numbers of pull-down and pull-up drivers in memory core arrays. Two 4-V internal Vcc converters are used separately for peripheral and core array circuits. The reference voltage generator employs a bandgap reference circuit whose temperature stability is better than conventional MOS diode references.

A jitter-tolerant 4.5 Gb/s CMOS interconnect for digital display

The digital display interface for flat panels is an emerging field that requires a robust high-speed interface for uncompromised picture quality, low cost, and low electromagnetic interference (EMI) in contrast to a very-wide digital-parallel interface. For a high-resolution display such as 1280/spl times/1024 pixels, more than 3.4 Gb/s of aggregate bandwidth is required over a 10 m cable. Since most graphic controllers synthesize the pixel clock to support various display resolutions, the pixel clock jitter exceeds more than 2 ns and the problem is further aggravated. The authors present an interconnect method for minimizing the effects of jitter in the pixel clock, thus improving the robustness of data recovery. The interconnect, comprising a transmitter and receiver, is fabricated with a 0.35 /spl mu/m CMOS process. A 100-pin TQFP package is used for both transmitter and receiver.

Interface states as an active component for 20 nm gate-length planar MOSFET with electrostatic channel extension (ESCE)

Electrostatic channel extension (ESCE) MOSFET, a transistor with static inversion layer formed by interface fixed charge is fabricated in planar bulk structure down to 20 nm gate-length. The 24 nm gate-length ESCE transistor with current 80 nm gate-length SRAM technology shows the excellent drive currents of 1.0 mA/mum with IOFF of 93 nA/mum at VDS = 1 V. Moreover, the ESCE transistor with the gate oxide thickness of 10 Aring shows effectively suppressed gate-oxide leakage, very low GIDL, high breakdown voltage (> 6 V), immunity from CD variance, and robust reliability. The ESCE scheme is very promising to overcome the scale-down limit of planar transistor beyond 20 nm with ultra-low cost