Won-suk Yang

Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations

We integrate FinFET DRAM in sub-60nm feature size. To avoid severe passing gate effects in FinFET cell array, we introduce a local damascene gate structure. Threshold voltage control of the ultra thin body transistors is successfully achieved by adopting p+ boron in-situ doped poly-silicon gate on the FinFET cells. As a result, very stable and uniform operation of FinFET cells is realized. The local damascene FinFET with p+ gate can become a highly feasible mainstream DRAM technology for sub-60nm low-power high-speed devices

A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-μm single-gate low-power SRAM device

A new double offset-implanted (DOI) technology, which can effectively suppress the gate-induced drain-leakage (GIDL) current of buried-channel PMOS transistor in small-size CMOS devices, is proposed and developed with a 0.12-/spl mu/m single-gate low-power SRAM device. The DOI scheme is characterized by the usage of the silicon nitride etch-stopper for the formation of borderless W-contact as offset spacer without supplementing auxiliary processes at p+ source/drain (S/D) implantation process after the n+ S/D one. It is assured that the DOI technology makes the gate-to-S/D overlap controllable, so that the GIDL current of PMOS transistor can remarkably be reduced. Furthermore, the enhancement of CMOS transistor performance was possible by reducing the sidewall reoxidation thickness of the gate-poly Si and optimizing the implantation conditions with this technology.

Characteristics of Cell Latch and Leakage Current at Standby State in 6-T Low-Power Static Random Access Memory (SRAM) Device

The standby current at device off-state is investigated against the measuring mode in 6-T and low-power static random access memory (SRAM) device with short gate length of 0.12 µm and high density of 32 M-bit. It can be found that there is the difference of the standby currents between initial and D0 modes and this discrepancy in the standby current is closely related to the leakage current of cell n-type metal-oxide semiconductor field-effect transistor (NMOSFET), especially pull-down transistor. This discrepancy in the standby currents among the measuring modes can be explained with the characteristic of the cell latch using its dependence on the leakage current of pull-down transistor and it will be shown that the cell spontaneously moves to minimize the standby current.

Effects of gate notching profile defect on characteristic of cell NMOSFET in low-power SRAM device

The effects of gate notching profile defects on transistor performance in cell NMOSFETs of low-power SRAM devices with 0.12 /spl mu/m channel length were investigated. Experimentally, it was found that gate notching profile defects cause serious degradation of the transconductance and the transistor drive current. TSUPREM4 simulations showed that the degradation of transistor characteristics is related to the penetration of the gate notching into the channel region over the source/drain (S/D) extension region and the rapid reduction of gate electric field. Moreover, we found that the degradation of transistor performance is more sensitive to notch depth than notch height.

Effects of gate notching profile defect on performance characteristics of short-channel NMOSFET with channel length of 0.12 μm

In this letter, we report the effects of gate notching on the performance characteristics of short-channel NMOS transistor with the gate oxide thickness of 32 /spl Aring/. The significant gate-notching defect into channel region brings about the serious degradation of such transistor performances as transconductance (G/sub m/) characteristic and subthreshold swing (S/sub t/), resulting in increases of threshold voltage (V/sub TH/) and leakage current (I/sub OFF/) and the considerable reduction of drive current (I/sub ON/). We will suggest the local thickening of gate oxide as a main mechanism of its effects and show that lack of gate-to-source/drain extension (SDE) overlap may be an additional reason for the degradation of I/sub ON/ with increasing the notch depth.