L. Zaid

Temperature Compensated 2.45 GHz Ring Oscillator with Double Frequency Control

A 2.4 GHz voltage controlled oscillator (VCO) with double frequency control has been designed using a CMOS 0.28 mum process for use in frequency synthesizer and open loop FSK modulation circuit in multi-band IEEE 802.15.4 wireless personal area network (PAN) applications. This double control allows the VCO to maintain its center frequency and tuning range throughout -40degC to 120degC. Simulations and measurements show the sensitivity of the VCO center frequency has been reduced from 1300 ppm/degC to 73 ppm/degC, while a phase noise of -96 dBc/Hz @ 1MHz offset with a power consumption of 18 mW have been achieved.

Frequency Synthesizer and FSK Modulator for IEEE 802.15.4 Based Applications

The feasibility of a low cost, 2.5 volts supply phase-locked loop for HomeRF application is demonstrated. Based on IEEE 802.15.4 specifications, this low power and low cost, multi-function PLL is used both in a single conversion receiver as frequency synthesizer and in a direct conversion transmitter as a frequency shift keying (FSK) modulator. Measurement results of the PLL and the open loop modulator together with VCO performances are presented. All the circuits have been fully integrated using 0.28 mum CMOS technology.

2.4-GHz frequency synthesizer with open loop FSK modulator for WPAN applications

The design of a low cost, low power multifunction phase-locked loop (PLL) for homeRF application is presented. This PLL is used in reception mode, as frequency synthesizer and in a direct conversion transmitter as a frequency shift keying (FSK) modulator in the transmit mode. Experimental results showing the circuit performances are presented. All the circuits, including the loop filter capacitance, have been fully integrated on chip using 0.13 mum CMOS technology.direct conversion transmitterfrequency shift keying modulatorloop filter capacitance,CMOS technology.

A CMOS adaptive RF front-end receiver for wireless applications

Design and implementation of an image-rejection double-quadrature radio frequency front-end receiver based on tunable polyphase filters (PPF) are presented in this article. The front-end consists of two sets of PPFs and a double-quadrature down-converter. The design contains devices that allow process spread and frequency drift control, making it suitable for multi-standard applications. Formal analysis and statistical method leading to the polyphase filter optimal sizing have been dealt with in this article. The effects of parasitic capacitances and component mismatch are also considered and discussed. Steps within CMOS polyphase filter design flow are then provided to guarantee high image rejection ratio (IRR) performance. The front-end receiver exhibits more than 60u2009dB IRR and good linearity in high-frequency applications.

Low-Gain-Wide-Range 2.4-GHz Phase Locked Loop

The feasibility of low noise sensitivity 2.4-GHz Phase Locked Loop for use in wireless communications as well as in clock generation circuit is demonstrated. The system uses low- gain-multi-band Voltage Controlled Oscillator which achieves a phase noise of -98 dBc/Hz @ 1MHz offset while a lock time of 150 - mus has been obtained from the PLL loop. The design has been implemented on standard CMOS technology.

A CMOS 2.45-GHz ring oscillator with temperature compensation

This paper presents a 2.45-GHz CMOS ring voltage-controlled oscillator (VCO) with a temperature compensation of the oscillation frequency. This compensation is achieved thanks to a biasing current proportional to absolute temperature (PTAT). This method allows to achieve temperature coefficient as low as 73 ppm/degC in -40degC to 120degC temperature range while saving phase-noise performance as well as power consumption of the oscillator. A detailed study of the all-CMOS proposed structure is performed. Simulation results obtained with 0.28 mum STMicroelectronics CMOS technology are presented.

FPGA-based programmable digital PLL with very high frequency resolution

A FPGA-based tunable all-digital control system featuring high resolution all-digital PLL is presented. The whole system has been designed under Simulink environment and synthesized with QuartusII. The system can achieve very high frequency resolution (0.1Hz) within a frequency range of 20kHz to 60MHz.

Design of fully-integrated RF front-end for large image rejection and wireless communication applications

A 2.4GHz image rejection (IR) radio-frequency front-end receiver is proposed in this paper. It adopts double-quadrature architecture with polyphase filters to achieve high image rejection ratio (IRR). A tunable polyphase filter topology that allows counteracting the process spread and frequency drifts, making it suitable for multi-standards applications, is also dealt with. The IR front-end, implemented in 130nm standard CMOS technology, ensures more than 60dB IRR and good linearity in high frequency applications.

Radio frequency tunable polyphase filter design

Polyphase filters are widely used in radio frequency (RF) receivers either to generate accurate quadrature signals or to reject the image. Analytical modeling of passive polyphase filter suitable for RF front-end applications is exposed. This analytical study has been used to calibrate the optimal values of passive components in order to obtain the maximum image rejection ratio (IRR). Component matching and parasitics reduction techniques have been taken into account. Tunable RC polyphase filter, suitable for multi-standard applications, has been fabricated in 0.13-µm CMOS technology.

A low-cost 2.45-GHz frequency synthesizer with open-loop modulation for WPAN applications

A low cost and low power frequency synthesizer Based on IEEE 802.15.4 specification using an optimized open-loop modulator is presented for Frequency Shift Keying modulation applications. The fully integrated synthesizer (0.166mm2) is implemented in a 0.28µm CMOS technology with 2.5V supply voltage. Measurements results of PLL lock time, open-loop frequency drift and demodulated signal are presented.