Lakshmanan Karuppiah

ILD0 CMP: Technology enabler for high K metal gate in high performance logic devices

The extension of Moores Law at the 45/32nm nodes is made possible by the introduction of high-k metal gate. In the gate-last scheme to integrate high-k metal gate, planarization and surface topography control have been reported as some of the biggest process challenges. This paper presents a three-platen chemical mechanical planarization process in which fixed abrasive is used on platen 2 and a non-selective slurry is used on platen 3 with a FullVision™ in-situ endpoint system. Superior planarization and dishing performance by the fixed abrasive and consistent endpoint control by FullVision enabled tight control of within wafer, within die and wafer-to-wafer thickness variations that is critical to the success of high k metal gate in high performance logic devices.

CMP for Copper TSV Applications

Through-silicon via (TSV) 3-D packaging and integration present many new opportunities and challenges for metals CMP applications. For front-side TSV polishing, challenges include the removal of large amounts of copper overburden, dishing control during copper clearing steps, and removal of large amounts of barrier metal and dielectric layers while still maintaining control over topography and defectivity. Additionally, the choice of barrier material can have significant impact on polishing in terms of the mechanical reliability regarding adhesion between the barrier metal and underlying dielectric layers. This paper will address many of these challenges with an emphasis on innovative technologies for superior process and endpoint controls, such as real-time profile control for thick copper films up to 6μm or more in thickness and automatic endpoint controls for barrier removal and dielectric stopping. The paper will also discuss some salient challenges for back-side TSV polishing, including the handling and polishing of bonded wafer pairs and strategies to minimize handling and polishing damage to the potentially fragile thinned device wafer. Additionally, the development of slurries with highly tunable copper-to-dielectric selectivity will be critical for enabling a wide range of final topographies, depending on requirements for subsequent bonding steps.

Post-CMP Cleaning of Copper/Hydrophobic Low-k Dielectric Films

The requirements for copper post-CMP cleaning include slurry particle removal, organic residue removal, metal contamination reduction, water mark elimination, copper corrosion prevention, and low-k surface change minimization. The difficulty in meeting some of these requirements varies with the CMP consumables (e.g. slurry, pad, etc.) used. Over the past ten years, the most significant factor driving changes in copper post-CMP cleaning is low-k surface hydrophobicity. A highly hydrophobic ultra low-k surface provides a significant challenge not only to wafer drying, but also to wafer cleaning and rinsing. In this paper, state-of-the-art post-CMP cleaning of Cu/ultra low-k dielectric films is presented.