You Wang

Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses

Spin transfer torque magnetic tunnel junction (STT MTJ) is considered as a promising candidate for non-volatile memories thanks to its low power, high speed and easy integration with CMOS process. However, it has been demonstrated intrinsically stochastic. This phenomenon leads to the frequent occurrence of switching errors, which results in considerable reliability issues of hybrid CMOS/MTJ circuits. This paper proposes a compact model of MTJ with STT stochastic behavior, in which technical variations and temperature evaluation are properly integrated. Moreover, the phenomenon of dielectric breakdown of MgO barrier which determines the lifetime of MTJ is also taken into consideration. Its accurate performances allow a more realistic reliability analysis involving the influences of ambient environment and technical process.

Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy

Magnetic tunnel junction nanopillar with interfacial perpendicular magnetic anisotropy (PMA-MTJ) becomes a promising candidate to build up spin transfer torque magnetic random access memory (STT-MRAM) for the next generation of non-volatile memory as it features low spin transfer switching current, fast speed, high scalability, and easy integration into conventional complementary metal oxide semiconductor (CMOS) circuits. However, this device suffers from a number of failure issues, such as large process variation and tunneling barrier breakdown. The large process variation is an intrinsic issue for PMA-MTJ as it is based on the interfacial effects between ultra-thin films with few layers of atoms; the tunneling barrier breakdown is due to the requirement of an ultra-thin tunneling barrier (e.g., <1 nm) to reduce the resistance area for the spin transfer torque switching in the nanopillar. These failure issues limit the research and development of STT-MRAM to widely achieve commercial products. In this paper, we give a full analysis of failure mechanisms for PMA-MTJ and present some eventual solutions from device fabrication to system level integration to optimize the failure issues.

Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology

In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes and normally-off electronics will need to meet constraints in speed, energy and robustness. This study focuses on NV logic-in-memory (LIM) architecture. Supply voltage (<inline-formula> <tex-math notation=LaTeX>

A novel circuit design of true random number generator using magnetic tunnel junction

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Robust magnetic full-adder with voltage sensing 2T/2MTJ cell

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Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core

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A Non-Monte-Carlo Methodology for Variability Analysis of Magnetic Tunnel Junction-Based Circuits

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MRAM-on-FDSOI Integration: A Bit-Cell Perspective

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Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning

</tex-math></inline-formula> scaling in NV circuits is proposed with design strategies, e.g., back-bias (BB), poly biasing (PB), and approximate computing. The design vector (<inline-formula> <tex-math notation=LaTeX>

Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device

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