Lakshmi Kanta Bera

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around nand p-FETs, fabricated using these stacked NW arrays as the channel (Lgges0.35 mum), exhibit excellent device performance with high ION/IOFF ratio (~106), near ideal subthreshold slope (~62-75 mV/dec) and low drain induced barrier-lowering (~20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate

AlGaN/GaN two-dimensional-electron gas heterostructures on 200 mm diameter Si(111)

This Letter reports on the epitaxial growth, characterization, and device characteristics of crack-free AlGaN/GaN heterostructures on a 200 mm diameter Si(111) substrate. The total nitride stack thickness of the sample grown by the metal-organic chemical vapor deposition technique is about 3.3 ± 0.1 μm. The structural and optical properties of these layers are studied by cross-sectional scanning transmission electron microscopy, high-resolution x-ray diffraction, photoluminescence, and micro-Raman spectroscopy techniques. The top AlGaN/GaN heterointerfaces reveal the formation of a two-dimensional electron gas with average Hall mobility values in the range of 1800 to 1900 cm2/Vs across such 200 mm diameter GaN on Si(111) samples. The fabricated 1.5 μm-gate AlGaN/GaN high-electron-mobility transistors exhibited the drain current density of 660 mA/mm and extrinsic transconductance of 210 mS/mm. These experimental results show immense potential of 200-mm diameter GaN-on-silicon technology for electronic devi...

Strained-Si heterostructure field effect devices

INTRODUCTION Heterostructure Field-Effect Devices Substrate Engineering Gate Dielectrics on Engineered Substrates Strained-Si Technology: Process Integration Nonclassical CMOS Structures Strain-Engineered Hetero-FETs: Modeling and Simulation STRAIN ENGINEERING IN MICROELECTRONICS Stress Induced during Manufacturing Global vs. Local Strain Substrate-Induced Strain Process-Induced Stress Stress/Strain Analysis STRAIN-ENGINEERED SUBSTRATES Epitaxy Heteroepitaxy and Strain Control Engineered Substrates: Technology Characterization of Strained Layers Engineered Substrates ELECTRONIC PROPERTIES OF ENGINEERED SUBSTRATES Substrate-Induced Strained-Si Carrier Lifetime Mobility: Thickness Dependence Mobility: Temperature Dependence Diffusion in Strained-Si Process-Induced Strained-Si Uniaxial vs. Biaxial Strain Engineering GATE DIELECTRICS ON ENGINEERED SUBSTRATES Strained-Si MOSFET Structures Thermal Oxidation of Strained-Si Rapid Thermal Oxidation Plasma Nitridation of Strained-Si Effect of Surface Roughness Effect of Strained-Si Layer Thickness High-k Gate Dielectrics on Strained-Si Gate Dielectrics on Ge HETEROSTRUCTURE SiGe/SiGeC MOSFETS SiGe/SiGeC:Material Parameters SiGe Hetero-FETs: Structures and Operation SiGe p-MOSFETs on SOI SiGeC Hetero-FETs SiGe-Based HEMTs Design Issues STRAINED-Si HETEROSTRUCTURE MOSFETS Operating Principle Uniaxial Stress: Process Flow Strained-Si MOSFETs with SiC-Stressor Biaxial Strain: Process Flow Scaling of Strained-Si MOSFETs Strained-Si MOSFETs: Reliability Industry Example: TSMC Industry Example: AMD MODELING AND SIMULATION OF HETERO-FETS Simulation of Hetero-FETs Modeling of Strained-SiMaterial Parameters Simulation of Strained-Si n-MOSFETs Characterization of Strained-Si Hetero-FETs TCAD: Strain-Engineered Hetero-FETs SPICE Parameter Extraction Performance Assessment Summaries and References appear in each chapter.

Random Telegraph Signal Noise in Gate-All-Around Si-FinFET With Ultranarrow Body

For the first time, the random telegraph signal (RTS) and its corresponding flicker noise (1/f) were investigated in gate-all-around p-type Si-FinFETs. For a device with gate width of ~ 100 nm (fin height) and length of ~ 200 nm, the typical RTS capture/emission time constants were ~ 0.1-1 ms. Very large RTS amplitudes (DeltaId/Id up to 25%) were observed, which is an effect attributable to the extreme device scaling and/or interface quality of FinFETs. The estimated scattering coefficients (alpha~10-12-10-13 ) are found to be higher than typical values obtained from MOSFETs. These findings demonstrate the relevance of RTS for FinFET operation

Three-Layer laminated metal gate electrodes with tunable work functions for CMOS applications

This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate electrodes consisting of three ultrathin (/spl sim/1-nm) layers, with metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO/sub 2/, followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800/spl deg/C-1000/spl deg/C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000/spl deg/C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000/spl deg/C.

Structural and optical properties of AlxGa1−xN/GaN high electron mobility transistor structures grown on 200 mm diameter Si(111) substrates

The authors report on the study of homogeneity in structural and optical properties of AlxGa1−xN/GaN high electron mobility transistor (HEMT) structures grown on 200 mm diameter Si(111) substrates. The consequence of a variation of buffer layer thicknesses as well as the interface quality has been studied by in-situ growth monitoring. A reasonably good uniformity of crystalline quality in the heterostructures grown with a lower wafer bowing has been observed from the full width at half maxima of symmetric as well as asymmetric high resolution x-ray diffraction scans across the wafer. Furthermore, the thickness and Al content of the AlxGa1−xN barrier layer across the wafer is found to be uniform when the wafer bowing is lower. Optical and electrical measurements across the epiwafer address the strain homogeneity, luminescence, and two-dimensional electron gas properties. Based on these studies of growth optimization, HEMT epiwafers with a total nitride stack thickness of 4.4 μm with a wafer bowing <50 μm on 1.0 mm thick Si substrates are demonstrated.The authors report on the study of homogeneity in structural and optical properties of AlxGa1−xN/GaN high electron mobility transistor (HEMT) structures grown on 200 mm diameter Si(111) substrates. The consequence of a variation of buffer layer thicknesses as well as the interface quality has been studied by in-situ growth monitoring. A reasonably good uniformity of crystalline quality in the heterostructures grown with a lower wafer bowing has been observed from the full width at half maxima of symmetric as well as asymmetric high resolution x-ray diffraction scans across the wafer. Furthermore, the thickness and Al content of the AlxGa1−xN barrier layer across the wafer is found to be uniform when the wafer bowing is lower. Optical and electrical measurements across the epiwafer address the strain homogeneity, luminescence, and two-dimensional electron gas properties. Based on these studies of growth optimization, HEMT epiwafers with a total nitride stack thickness of 4.4 μm with a wafer bowing <50 μm o...

Extraction of physical parameters of strained silicon MOSFETs from C-V measurement

This paper presents a methodology for extraction of the physical parameters of strained-silicon MOSFET from one capacitance-voltage (C-V) measurement based on physics-based compact model and conventional C-V characterization techniques. The extracted physical parameters (such as strained-silicon layer thickness and doping as well as conduction band offset) are used to create a numerical (Medici) device structure, from which the simulated C-V data is compared with the measured data as well as that from the compact model (Xsim), which validates the extraction technique. The proposed approach provides a simple yet physical means to probe into strained-silicon MOSFFET structures useful for characterize and model these devices, which are emerged as promising candidates for the enhancement and extension to conventional bulk-Si CMOS technology.

Comparison of the Al x Ga 1– x N/GaN Heterostructures Grown on Silicon-on-Insulator and Bulk-Silicon Substrates

Compared with bulk-Si wafer, AlxGa1-xN/gallium nitride (GaN) heterostructures grown on a 150-mm silicon-on-insulator (SOI) substrate with a 35-nm-thick Si overlayer are shown to have ~50% less wafer bowing. As a result, the 2-D electron gas mobility and the sheet-resistivity uniformity on SOI are improved due to a lower defect density. In terms of device performance, high-electron-mobility transistors (HEMTs) fabricated on the AlxGa1-xN/GaN-on-SOI exhibit ~20.5% higher saturation drain current as compared with the bulk-Si counterparts. However, due to the poorer conductivity of the buried oxide layer, the AlxGa1-xN/GaN-on-SOI HEMT suffers greater self-heating, with ~50 K higher channel temperature. With mitigation of self-heating, the AlxGa1-xN/GaN-on-SOI, in view of its more superior structural and thermal stability, should offer an attractive alternative for integration of the GaN technology with the Si CMOS platform.

Gold-free contacts on AlxGa1-xN/GaN high electron mobility transistor structure grown on a 200-mm diameter Si(111) substrate

The authors report on the fabrication and characterization of low-temperature processed gold-free Ohmic contacts for AlxGa1−xN/GaN high electron mobility transistors (HEMTs). The HEMT structure grown on a 200-mm diameter Si(111) substrate is used in this study. Using the Ti/Al/NiV metal stack scheme, the source/drain Ohmic contact optimization is accomplished through the variation of Ti/Al thickness ratio and thermal annealing conditions. For an optimized Ti/Al stack thickness (20/200 nm) annealed at 500 °C for 30 s with smooth contact surface morphology, a specific contact resistivity of ∼6.3 × 10−6 Ω cm2 is achieved. Furthermore, with gold-free Ni/Al gates, the fabricated HEMTs exhibit ION/IOFF ratio of ∼109 and a subthreshold swing of ∼71 mV/dec. The demonstrated gold-free contact schemes thus provide a solution toward the implementation of GaN-based HEMT process on a Si foundry platform.