Lawrence Griffith Heller

Overview of CCD memory

This paper summarizes the status and potential of charge-coupled device (CCD) memories. Cost-performance tradeoffs for serial memories are reviewed, and the CCD chip organizations for slow and fast access systems are discussed. Comparisons are made between CCD and MOS random access memory (RAM) chips on the basis of cell area, support circuits, cell operation, and technology.

Experimental 2.0 V power/performance optimization of a 3.6 V-design CMOS microprocessor-PowerPC 601

An experimental 2.0 V PowerPC 601 microprocessor demonstrating 3/spl times/ active power reduction and performance comparable to the 3.6 V version has been fabricated. The standard 3.6 V 0.6 /spl mu/m CMOS technology was modified for low-power operation with unmodified circuits/masks. No degradation to yield was observed. Experimental low-voltage PowerPC 601 process/device alterations and test results are described.<<ETX>>

Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

An experimental 2.0*volt low-power PowerPC 601TM Microprocessor built In a modified 3.6-volt, 0.6-tim IBiUI CMOS technology Is described. By using unmodified masks from the 3.6-volt design, a 3x power savings was realized while maintaining nearly the original performance. The use of selective scaling provides high performance at reduced power supply voltage. This technique, applicable to selected existing product designs, may allow early entry into the low-power marlcet while minimizing new process development expense. The technique proposes hyperscaled reductions in specific electrical and physical parameters, while keeping horizontal layout rules unchanged. Static chip designs, which comprise the majority of 601 circuitry, respond well to the alterations. In addition, potential reliability detractors are reduced or eliminated. Challenges to this technique include I/O Interfacing and minimizing leakages associated with low device thresholds. The 601 design and its base technology are described, along with the experimental changes. The paper reviews the motivation behind lowpower microprocessor development, alternative power-saving techniques being practiced, and opportunities for continued power reduction.