Zong-Hao Ye

A higher-k tetragonal HfO2 formed by chlorine plasma treatment at interfacial layer for metal-oxide-semiconductor devices

A tetragonal HfO2 (t-HfO2) with higher-k value and large band gap is investigated in this work. X-ray diffraction analysis shows a t-HfO2 can be formed by using Cl2 plasma treatment at the HfO2/Si interface after a post deposition annealing at 650 °C. The mechanisms of t-HfO2 formation can be attributed to the Si diffusion and oxygen vacancy generation which are formed by Cl2 plasma treatment. From the cross-sectional transmission electron microscope and capacitance-voltage measurement, the k value of this t-HfO2 is estimated to be about 35. The optical band gap value for t-HfO2 is similar to that of the monoclinic.

Enhanced Operation in Charge-Trapping Nonvolatile Memory Device With

A stacked Si₃N₄/HfO₂ charge-trapping (CT) layer was proposed to improve erase operation and retention for CT nonvolatile memory (NVM) devices. The improvement can be attributed to the smaller valence band offset of Si₃N₄ to Si and the higher barrier for electron detrapping from HfO₂ to Si₃N₄. The programming and retention characteristics of CT NVM devices can be further enhanced by inserting Al₂O₃ between Si₃N₄ and HfO₂ as the CT layer. This is because most of the injecting charges are trapped at the Si₃N₄/Al₂O₃ interface, and Al₂O₃ also provides a high barrier for electron detrapping.

\hbox{Si}_{3}\hbox{N}_{4}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{HfO}_{2}

Charge-trapping (CT) flash memory devices with Ge channel are studied for the first time. The operation characteristics of Ge-channel devices with different interfacial layers (IL), including GeO2, GeON, and AlON, are investigated. The programming/erasing speeds of devices with Ge channel can be significantly improved as compared with those with Si or SiGe channel. The retention properties of Ge-channel CT flash devices are much enhanced with a stacked tunneling layer formed by the low-temperature processes. However, the endurance characteristics of Ge-channel devices need improvement as compared with those of Si-channel devices. This may be resolved by a high-quality IL formed with an electron cyclotron resonance system and passivated with a H2 treatment.

Charge-Trapping Layer

Although retention characteristic of charge trapping (CT) flash device is improved by using Al<inf>2</inf>O<inf>3</inf>/HfO<inf>2</inf> blocking layer, the electron back tunneling (EBT) during erasing is still an issue. In order to overcome this issue, CT flash devices with triple blocking layers of either high/low/high (HLH) or low/high/low (LHL) electron energy barrier structures are proposed in this work. Programming, erasing, and retention characteristics of CT flash device can be enhanced by these triple blocking layers. In addition, CT flash device with Al<inf>2</inf>O<inf>3</inf>/HfAlO/Al<inf>2</inf>O<inf>3</inf> triple blocking layer has the most excellent data retention and good programming speed.

Enhanced Programming and Erasing Speeds of Charge-Trapping Flash Memory Device With Ge Channel

The equivalent oxide thickness in Ge MOS device is scaled down to 0.39 nm, and the leakage current is decreased as well. The improvement can be attributed to the in-situ Ge sub-oxide desorption process in an ALD chamber at 370 ^°C. About 95% Ge⁴⁺ in HfGeO_x interfacial layer are obtained by H₂O plasma process together with in-situ desorption before atomic layer deposition.

Effects of triple blocking layers on operation performance in charge-trapping flash devices

Two approaches are proposed in this work to improve the operation characteristics of charge-trapping (CT) flash devices, namely, SiGe buried channel and stacked charge-trapping layer. SiGe buried channel with different Ge contents and various thicknesses of Si-cap layer on operation characteristics of CT flash devices were studied. The programming and erasing speeds of CT flash devices are significantly improved by employing SiGe buried channel. The retention properties of CT flash devices are satisfactory with suitable Ge content in SiGe buried channel and proper thickness of Si-cap layer. Moreover, the programming and erasing speeds of CT flash devices are significantly improved by applying Si<inf>3</inf>N<inf>4</inf>/Hf<inf>x</inf>Al<inf>1−x</inf>O charge trapping layers due to the enhanced carrier capture efficiency with extra interface (Si<inf>3</inf>N<inf>4</inf>/Hf<inf>x</inf>Al<inf>1−x</inf>O). The retention property is clearly improved as well.

Very low EOT and high oxidation state interfacial layer in Ge MOS devices

Although enhancement on electrical properties of flash devices with HfAlO charge trapping layer has been reported, there are still serious problems in retention characteristics. In this work, a charge-trapping (CT) flash device with Si<inf>3</inf>N<inf>4</inf>/Hf<inf>x</inf>Al<inf>1−x</inf>O as charge trapping layer is presented. Experimental results show that the program/erase speeds of the proposed devices can be enhanced and the retention characteristic is improved as well.