Loke Kun Tan

A 200 MHz quadrature digital synthesizer/mixer in 0.8 /spl mu/m CMOS

A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc. The frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles. The chip is also capable of frequency, phase, and quadrature amplitude modulation. These modulation capabilities operate up to the maximum clocking frequency. The chip provides the capability of parallel operation of multiple chips with throughputs up to 800 MHz. The 0.8 /spl mu/m triple level metal N-well CMOS chip has a complexity of 52000 transistors with a core area of 2.6/spl times/6.1 mm/sup 2/. Power dissipation is 2 W at 200 MHz and 5 V. >

A 70 Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10 b ADC and FEC decoder

A variable-rate IF-sampled QAM receiver integrated circuit operates at symbol rates from 1 to 7 MBaud in 4, 16, 32, 64, 128, 256, and 1024-QAM. The QAM receiver is a monolithic mixed-signal device implemented in a 0.5 /spl mu/m triple-level metal single-poly CMOS process. The device incorporates a 10b A/D converter, analog PLLs, interpolating demodulator, square-root raised cosine receive filters, timing/carrier recovery loops, 20-tap complex equalizer, and a Reed-Solomon forward error correction (FEC) decoder that is compliant with European digital video broadcasting (DVB) and Digital Audio-Visual Council (DAVIC) standards. Applications of this QAM receiver include digital cable-TV set-top terminals, cable modems, and digital microwave radios.

An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 /spl mu/m CMOS

Direct digital frequency synthesizers (DDFS) play an important role in modern digital communications and instrumentation. They offer many advantages including fast continuous-phase switching response, fine frequency resolution, large bandwidth, good spectral purity, and low phase noise. The architecture in this design uses a phase accumulator to address a ROM look-up table that stores the sine samples. The input word (frequency-control word) to the phase accumulator controls the frequency of the generated sine waveform. This chip has modulation capabilities that include frequency modulation and phase modulation. Frequency modulation is performed by directly modulating the frequency control word and phase modulation is obtained by adding a phase offset to the phase accumulator output before addressing the ROM look-up table. The 7.2/spl times/7.9 mm/sup 2/ 94,000 transistor chip dissipates 3 W at 5 V and 800 MHz.

A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization

This paper introduces multiplying digital-to-analog converter (MDAC) equalization, a digital correction technique for pipeline ADCs that corrects MDAC gain, settling, and other dynamic errors using successive digital FIR filters operating on sub-ADC output samples. This technique reduces the required MDAC residue amplifier (RA) bandwidth relative to the sampling frequency, thereby reducing ADC power. MDAC equalization is demonstrated in a 240-mW 2.1-GS/s ping-pong pipeline ADC in 40-nm CMOS where MDAC RA power is reduced from 175 to 53 mW by 70%. The ADC achieves 58 dB SNR and 52 dB SNDR.

A 2.7 mW/Channel 48–1000 MHz Direct Sampling Full-Band Cable Receiver

A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing functionalities and enhancing performances, including digital automatic gain control (AGC), digital phase-locked loop (PLL), and digital ADC compensation. The receiver is capable of receiving 158 256 QAM channels from 48 to 1000 MHz simultaneously, achieving up to 10 Gb/s data throughput for data and video while exceeding Data over cable service interface specification (DOCSIS) and Society of Cable Telecommunications Engineers (SCTE) requirements. The CMOS receiver occupies 1 mm2 area while consuming 300 mW. The LNA consumes 130 mW and occupies 3 mm2 area. The total power dissipation from the receiver is 2.7 mW per 6 MHz channel when capturing the entire cable spectrum.

Correction to "A 70-Mb/s Variable-Rate 1024-QAM Cable Receiver IC with Integrated 10-b ADC and FEC Decoder"

In the above-named article, there was an error in Fig. 23, which appeared on page 2217. The bottom portion of the figure was corrupted during production. The correct figure is presented.