Binning Chen

A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization

This paper introduces multiplying digital-to-analog converter (MDAC) equalization, a digital correction technique for pipeline ADCs that corrects MDAC gain, settling, and other dynamic errors using successive digital FIR filters operating on sub-ADC output samples. This technique reduces the required MDAC residue amplifier (RA) bandwidth relative to the sampling frequency, thereby reducing ADC power. MDAC equalization is demonstrated in a 240-mW 2.1-GS/s ping-pong pipeline ADC in 40-nm CMOS where MDAC RA power is reduced from 175 to 53 mW by 70%. The ADC achieves 58 dB SNR and 52 dB SNDR.

A 240mW 2.1GS/s 12b pipeline ADC using MDAC equalization

This paper introduces MDAC equalization, a digital correction technique for pipeline ADCs that corrects MDAC gain and settling errors using successive digital FIR filters operating on sub-ADC output samples. This technique reduces the required MDAC residue amplifier (RA) bandwidth relative to the sampling frequency, thereby reducing ADC power. MDAC equalization is demonstrated in a 240mW 2.1GS/s 12b ping-pong pipeline ADC in 40nm CMOS where MDAC RA power is reduced from 175mW to 53mW by 70%.

A 2.7 mW/Channel 48–1000 MHz Direct Sampling Full-Band Cable Receiver

A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing functionalities and enhancing performances, including digital automatic gain control (AGC), digital phase-locked loop (PLL), and digital ADC compensation. The receiver is capable of receiving 158 256 QAM channels from 48 to 1000 MHz simultaneously, achieving up to 10 Gb/s data throughput for data and video while exceeding Data over cable service interface specification (DOCSIS) and Society of Cable Telecommunications Engineers (SCTE) requirements. The CMOS receiver occupies 1 mm2 area while consuming 300 mW. The LNA consumes 130 mW and occupies 3 mm2 area. The total power dissipation from the receiver is 2.7 mW per 6 MHz channel when capturing the entire cable spectrum.

A Full-Band processor for reduction of RF mixer LO harmonic images

A Full-Band Capture (FBC) Harmonic Rejection Canceler (HRC) processor is presented. This processor consists of an RF low-noise preamplifier, a 2700 Msamp/s 6-bit flash ADC, a digital channelizer which selects one or more interfering RF channels, and an adaptive canceler. This canceler removes the interference caused by strong blockers that may be inadvertently folded onto the desired channel by local oscillator (LO) harmonics or spurs. This processor digitizes the entire cable or broadcast television spectrum from 50-1000 MHz and can adaptively cancel folded blocker interference from anywhere within this range. An image reduction of at least 23dB was measured. The processor is embedded within an integrated 40nm CMOS DVB-T2 TV receiver including tuner, demodulator and FEC. The complete embedded RF/analog/DSP HRC processor has an area of 0.38 mm2 and uses 205 mW.

A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver

We present a direct sampling full-band capture receiver for cable and digital TV applications. It consists of a 28nm CMOS ADC-based direct sampling receiver and a 0.18um BiCMOS LNA. It is capable of receiving 158 channels from 48MHz to 1000MHz simultaneously, achieving up to 10Gb/s data throughput, while exceeding DOCSIS requirements. The CMOS receiver occupies 1mm2 area while consuming 300mW. The LNA consumes 130mW. The total power dissipation from the receiver is 2.7mW per 6MHz channel.