Seyed Ruhollah Shojaii

CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments

Pixel detectors at HL-LHC experiments or other future experiments are facing new challenges, especially in terms of unprecedented levels of radiation and particle flux. This paper describes the progress made by the CHIPIX65 project of INFN for the development of a new generation readout ASIC using CMOS 65 nm technology.

RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC

Natale Demaria∗† INFN Sezione di Torino, Torino, Italy E-mail: demaria@to.infn.it F.Ciciriello, F.Corsi, C.Marzocca Politecnico di Bari, Bari, Italy G.De Robertis, F.Loddo, C.Tamma INFN Sezione di Bari, Bari, Italy V.Liberali, S.Shojaii, A.Stabile INFN Sezione di Milano and Universita degli Studi di Milano, Milano, Italy M.Bagatin, D.Bisello, S.Gerardin, S.Mattiazzo, L.Ding, P.Giubilato, A.Paccagnella INFN Sezione di Padova and Universita di Padova, Padova, Italy F.De Canio, L.Gaioni, M.Manghisoni, V.Re, G.Traversi, E.Riceputi INFN Sezione di Pavia and Universita di Bergamo, Bergamo, Italy L.Ratti, C.Vacchi INFN Sezione di Pavia and Universita di Pavia, Pavia, Italy R.Beccherle, G.Magazzu, F.Morsani, F.Palla INFN Sezione di Pisa, Pisa, Italy G.M.Bilei, M.Menichelli INFN Sezione di Perugia, Perugia, Italy E.Conti, S.Marconi, D.Passeri, P.Placidi INFN Sezione di Perugia and Department of Engineering, Universita di Perugia, Italy G.Dellacasa, G.Mazza, A.Rivetti, M.D.Da Rocha Rolo INFN Sezione di Torino, Torino, Italy E.Monteil, L.Pacher INFN Sezione di Torino and University of Torino, Torino, Italy

Heterogeneous computing system platform for high-performance pattern recognition applications

we present a system architecture made of a motherboard with a Xilinx Zynq System on Chip (SoC) and a mezzanine board equipped with an Associative Memory chip (AM). The proposed architecture is designed to serve as an accelerator of general purpose algorithms based on pipeline processing and pattern recognition. We present the open source software and firmware developed to fully exploit the available communication channels between the ARM CPU and the FPGA using Direct Memory Access (DMA) technique and the AM using Multi-Gigabit Transceivers (MGT). We report the measured performances and discuss potential applications and future developments. The proposed architecture is compact, portable and provide a large communication bandwidth between components.

Improvement of radiation tolerance in CMOS ICs through layout-oriented simulation

This paper proposes a methodology to design radiation-hardened ICs, suitable for space applications and high-energy physics experiments. The miniaturization of ICs has brought an increase of circuit logic errors due to radiation, also at ground level. The increased complexity of IC design due to technology scaling requires new tools to design rad-hard circuits. In this paper, we propose a design tool that employs a layout-oriented simulation approach to identify the sensitive IC area and provide data about the effects due to radiation. The simulation tool is implemented in Cadence LayoutGXL. The proposed approach will help to have a more efficient IC design reducing design time and costs related to the need of fabricating prototypes to be characterized under radiation to test their hardness.

Double-redundant design methodology to improve radiation hardness in pixel detector readout ICs

This paper proposes a new design method to enhance the radiation hardness of circuits for the next generation of pixel detectors in High Energy Physics experiments. The approach is based on Radiation Hardness By Design methodology to mitigate Single Event Effects. In particle detectors, front-end electronics opeates in an environment characterized by a high dose of radiation. We propose a set of digital cells specifically designed to tolerate a high level of radiation (up to 1 Grad). The cells have been designed in 65 nm CMOS technology. Simulation results show the complete functionality up to 1 Grad of total dose of radiation. The first prototype chip has been designed and submitted for fabrication under the Istituto Nazionale di Fisica Nucleare (INFN) CHIPIX65 project.

A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications

In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks: a 6T SRAM, and a 4T XOR logic gate. Each XORAM cell makes a bitwise comparison between input data and stored data. The memory is organized in 18-bit words, and all the 18 XOR outputs bits must have a low logic value to trigger a high logic value of the single bit match line. A 18-input NOR gate performs this operation. The memory operation is triggered by the change of the least significant bit of the 18-bit input word, which is delayed w.r.t. the other bits. In this way, the logic does not require any clock. The proposed architecture is based on CMOS combinational logic, and it does not require any precharge operation, nor control and timing logic. The Associative Memory block is useful for several pattern recognition tasks, such as track recognition in high energy physics experiments, and image recognition for medical applications.