A. Annovi

The fast tracker processor for hadronic collider triggers

Perspective for precise and fast track reconstruction in future hadronic collider experiments are addressed. We discuss the feasibility of a pipelined highly parallelized processor dedicated to the implementation of a very fast algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points (patterns) for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at a rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above few GeV and search secondary vertexes within typical level-2 times.

The fast tracker processor for hadron collider triggers RID C-4866-2008

Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times.

A pipeline of associative memory boards for track finding RID C-4866-2008

We present a pipeline of associative memory boards for track finding, which satisfies the requirements of level two triggers of the next Large Hadron Collider experiments. With respect to previous realizations, the pipelined architecture warrants full scalability of the memory bank, increased bandwidth (by one order of magnitude), and increased number of detector layers (by a factor of two). Each associative memory board consists of four smaller boards, each containing 32 programmable associative memory chips, implemented with a low-cost commercial field-programmable gate array (FPGA). FPGA programming has been optimized for maximum efficiency in terms of pattern density, while printed circuitboard design has been optimized in terms of modularity and FPGA chip density. A complete associative memory board has been successfully tested at 40 MHz; it can contain 7.2/spl times/10/sup 3/ particle trajectories.

The "Road Warrior" for the CDF online silicon vertex tracker

The Online Silicon Vertex Tracker (SVT) is a new trigger processor dedicated to the 2-D reconstruction of charged particle trajectories at the level 2 of the CDF trigger. The SVT links the digitized pulse heights found within the Silicon Vertex Detector to the tracks reconstructed in the Central Outer Tracker by the level 1 Fast Track Finder. The SVT was recently modified in order to increase its efficiency. The new configuration uses all the Silicon Vertex detector layers. On the other hand the processing time has increased. This can be a problem at higher luminosities of the Tevatron. The Road Warrior is a new board that, eliminates redundant track candidates before the Track Fitting. It is based on the principle of the Associative Memory. The algorithm used is described in the paper, as well as the hardware implementation.

A fast FPGA-based clustering algorithm for real time image processing2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC)

Real time image analysis has undergone a rapid development in the last few years, due to the increasing availability of low cost computational power. However computing power is still a limit for some high quality applications. Highresolution medical image processing, for example, are strongly demanding for both memory (~250 MB) and computational capabilities allowing for 3D processing in affordable time. We propose the reduction of execution time of image processing exploiting the computing power of parallel arrays of Field Programmable Gate Arrays (FPGAs). We apply this idea to an algorithm that finds clusters of contiguous pixels above a certain programmable threshold and process them to produce measurements that characterize their shape. It is a fast general-purpose algorithm for high-throughput clustering of data with a two dimensional organization. The two-dimensional problem is well processed by FPGAs since their available logic is naturally organized into a 2-dimensional array. The algorithm is designed to be implemented with FPGAs but it can also profit of cheaper custom electronics. The key feature is a very short processing time that scales linearly with the amount of data to be processed. This means that clustering can be performed in pipeline with the image acquisition, without suffering from combinatorial delays due to looping multiple times through the whole amount of data.

Associative memory design for fast tracker at LHC2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC)

We propose a new generation of VLSI processor for pattern recognition based on Associative Memory architecture, optimized for on-line track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new R&D Associative Memory project: it maximizes the pattern density on ASICs and improves the functionality for the Fast Tracker (FTK) proposed to upgrade the ATLAS trigger at LHC. Finally we will focus on possible future applications inside and outside High Physics Energy (HEP).