Luca Grella

REBL: design progress toward 16 nm half-pitch maskless projection electron beam lithography

REBL (Reflective Electron Beam Lithography) is a novel concept for high speed maskless projection electron beam lithography. Originally targeting 45 nm HP (half pitch) under a DARPA funded contract, we are now working on optimizing the optics and architecture for the commercial silicon integrated circuit fabrication market at the equivalent of 16 nm HP. The shift to smaller features requires innovation in most major subsystems of the tool, including optics, stage, and metrology. We also require better simulation and understanding of the exposure process. In order to meet blur requirements for 16 nm lithography, we are both shrinking the pixel size and reducing the beam current. Throughput will be maintained by increasing the number of columns as well as other design optimizations. In consequence, the maximum stage speed required to meet wafer throughput targets at 16 nm will be much less than originally planned for at 45 nm. As a result, we are changing the stage architecture from a rotary design to a linear design that can still meet the throughput requirements but with more conventional technology that entails less technical risk. The linear concept also allows for simplifications in the datapath, primarily from being able to reuse pattern data across dies and columns. Finally, we are now able to demonstrate working dynamic pattern generator (DPG) chips, CMOS chips with microfabricated lenslets on top to prevent crosstalk between pixels.

REBL nanowriter: Reflective Electron Beam Lithography

REBL (Reflective Electron Beam Lithography) is being developed for high throughput electron beam direct write maskless lithography. The system is specifically targeting 5 to 7 wafer levels per hour throughput on average at the 45 nm node, with extendibility to the 32 nm node and beyond. REBL incorporates a number of novel technologies to generate and expose lithographic patterns at estimated throughputs considerably higher than electron beam lithography has been able to achieve as yet. A patented reflective electron optic concept enables the unique approach utilized for the Digital Pattern Generator (DPG). The DPG is a CMOS ASIC chip with an array of small, independently controllable cells or pixels, which act as an array of electron mirrors. In this way, the system is capable of generating the pattern to be written using massively parallel exposure by ~1 million beams at extremely high data rates (~ 1Tbps). A rotary stage concept using a rotating platen carrying multiple wafers optimizes the writing strategy of the DPG to achieve the capability of high throughput for sparse pattern wafer levels. The exposure method utilized by the DPG was emulated on a Vistec VB-6 in order to validate the gray level exposure method used in REBL. Results of these exposure tests are discussed.

REBL: A novel approach to high speed maskless electron beam direct write lithography

The system concepts used in a novel approach for a high throughput maskless lithography system called reflective electron beam lithography (REBL) are described. The system is specifically targeting five to seven wafer levels per hour throughput on average at the 45nm node, with extendibility to the 32nm node and beyond. REBL incorporates a number of novel technologies to generate and expose lithographic patterns at estimated throughputs considerably higher than electron beam lithography has been able to achieve as yet. A patented reflective electron optic concept enables the unique approach utilized for the digital pattern generator (DPG). The DPG is a complementary metal oxide semiconductor application specific integrated circuit chip with an array of small, independently controllable metallic cells or pixels, which act as an array of electron mirrors. In this way, the system is capable of generating the pattern to be written using massively parallel exposure by ∼1×106 beams at extremely high data rates ...

Reflective electron beam lithography: A maskless ebeam direct write lithography approach using the reflective electron beam lithography concept

Reflective electron beam litography (REBL) utilizes several novel technologies to generate and expose lithographic patterns at throughputs that could make ebeam maskless lithography feasible for high volume manufacturing. The REBL program was described in a previous article [P. Petric et al., J. Vac. Sci. Technol. B 27, 161 (2009)] 2 years ago. This article will review the system architecture and the progress of REBL in the past 2 years. The main technologies making REBL unique are the reflective electron optics, the rotary stage, and the dynamic pattern generator (DPG). Changes in how these concepts have been implemented in a new design will be discussed. The main disadvantage of today’s electron beam direct write is low throughput; it takes many tens of hours to expose a 300 mm wafer today using ebeam lithography. The projected system throughput performance with the integrated technology of the reflective optics, DPG, and a multiple wafer rotary stage will be shown incorporating the performance data for the new column design.Reflective electron beam litography (REBL) utilizes several novel technologies to generate and expose lithographic patterns at throughputs that could make ebeam maskless lithography feasible for high volume manufacturing. The REBL program was described in a previous article [P. Petric et al., J. Vac. Sci. Technol. B 27, 161 (2009)] 2 years ago. This article will review the system architecture and the progress of REBL in the past 2 years. The main technologies making REBL unique are the reflective electron optics, the rotary stage, and the dynamic pattern generator (DPG). Changes in how these concepts have been implemented in a new design will be discussed. The main disadvantage of today’s electron beam direct write is low throughput; it takes many tens of hours to expose a 300 mm wafer today using ebeam lithography. The projected system throughput performance with the integrated technology of the reflective optics, DPG, and a multiple wafer rotary stage will be shown incorporating the performance data for...

Sub-50-nm isolated line and trench width artifacts for CD metrology

We present a technique to produce isolated lines and trenches with arbitrary widths in the range of 12 nm to 500 nm, arbitrary heights and depths in the range of 100 nm to 2 μm, 90-degree sidewall angle, and top corner radii as small as 5 nm. These structures are ideal candidates as Critical Dimension (CD) absolute standards. The sidewall angle can further be varied to create an arbitrary sidewall angle that can be accurately measured.

Three-dimensional simulation of top down scanning electron microscopy images

Low voltage scanning electron microscopy (SEM) metrology and inspection are performed by immersing the sample in an electric field; under this condition, when a scanning electron beam images a sample containing insulating features (like oxides and resist), a surface global charge builds up to offset the applied field and a transverse local field will form as a result of the scanning beam. The surface global charge is responsible for the voltage contrast and imaging properties, while local fields degrade image resolution. In this article we describe a simulation approach able to explain the imaging properties of charged surfaces and how resolution is affected by local fields. Using electron ray tracing in the column, the simulation follows both the emitted and primary electron trajectories outside the sample. In addition, Monte Carlo scattering simulation calculates the electron trajectory and charge deposition inside the sample. The resulting charge density is used to calculate the field inside and outsid...

The REBL DPG: recent innovations and remaining challenges

Reflective electron-beam lithography (REBL) employs a novel device to impress pattern information on an electron beam. This device, the digital pattern generator (DPG), is an array of small electron reflectors, in which the reflectance of each mirror is controlled by underlying CMOS circuitry. When illuminated by a beam of low-energy electrons, the DPG is effectively a programmable electron-luminous image source. By switching the mirror drive circuits appropriately, the DPG can ‘scroll’ the image of an integrated circuit pattern across its surface; and the moving electron image, suitably demagnified, can be used to expose the resist-coated surface of a wafer or mask. This concept was first realized in a device suitable for 45 nm lithography demonstrations. A next-generation device has been designed and is presently nearing completion. The new version includes several advances intended to make it more suitable for application in commercial lithography systems. We will discuss the innovations and compromises in the design of this next-generation device. For application in commercially-practical maskless lithography at upcoming device nodes, still more advances will be needed. Some of the directions in which this technology can be extended will be described.

Digital pattern generator: an electron-optical MEMS for massively parallel reflective electron beam lithography

Abstract. The digital pattern generator (DPG) is a complex electron-optical MEMS that pixelates the electron beam in the reflective electron beam lithography (REBL) e-beam column. It potentially enables massively parallel printing, which could make REBL competitive with optical lithography. The development of the REBL DPG, from the CMOS architecture, through the lenslet modeling and design, to the fabrication of the MEMS device, is described in detail. The imaging and printing results are also shown, which validate the pentode lenslet concept and the fabrication process.

New advances with REBL for maskless high-throughput EBDW lithography

REBL (Reflective Electron Beam Lithography) is a program for the development of a novel approach for highthroughput maskless lithography. The program at KLA-Tencor is funded under the DARPA Maskless Nanowriter Program. A DPG (digital pattern generator) chip containing over 1 million reflective pixels that can be individually turned on or off is used to project an electron beam pattern onto the wafer. The DARPA program is targeting 5 to 7 wafers per hour at the 45 nm node, and this paper will describe improvements to both increase the throughput as well as extend the system to the 2x nm node and beyond. This paper focuses on three specific areas of REBL technology. First, a new column design has been developed based on a Wien filter to separate the illumination and projection beams. The new column design is much smaller, and has better performance both in resolution and throughput than the first column which used a magnetic prism for separation. This new column design is the first step leading to a multiple column system. Second, the rotary stage latest results of a fully integrated DPG CMOS chip with lenslets will be reviewed. An array of over 1 million micro lenses which is fabricated on top of the CMOS DPG chip has been developed. The microlens array eliminates crosstalk between adjacent pixels, maximizes contrast between on and off states, and provides matching of the NA between the DPG reflector and the projection optics.

Three dimensional simulations of SEM imaging and charging

SEM based CD control and wafer inspection has an increasingly active role in the semiconductor industry. Current design rules require a CD control with a precision in the nanometer range. In order to achieve this precision, a complete model of the image formation mechanism is desirable. For this reason we present a three-dimensional simulation of scanning electron microscope (SEM) images. The simulations include Monte Carlo electron scattering, charging in the substrate and electron ray-tracing in the column. We investigate some specific cases in CD-SEM metrology: We will describe the effect of scan orientation relative to the orientation of the imaged feature on the apparent beam width (ABW), the effect of magnification on contact imaging, and the effect of residue in resist trenches. Our results, regarding these examples, clearly indicate that a fully three-dimensional numerical simulation is needed to obtain an understanding of image formation and resolution limiting factors.